Inhaltszusammenfassung zur Seite Nr. 1
PRELIMINARY
CY14B101P
1 Mbit (128K x 8) Serial SPI nvSRAM
with Real Time Clock
■ Write Protection
Features
❐ Hardware Protection using Write Protect (WP) Pin
■ 1 Mbit NonVolatile SRAM
❐ Software Protection using Write Disable Instruction
❐ Internally organized as 128K x 8
❐ Software Block Protection for 1/4, 1/2, or entire Array
®
❐ STORE to QuantumTrap nonvolatile elements initiated
® ■ Low Power Consumption
automatically on power down (AutoStore ) or by user using
❐ Single 3V +20%, –10% op
Inhaltszusammenfassung zur Seite Nr. 2
CY14B101P PRELIMINARY Pinouts Figure 1. Pin Diagram - 16-Pin SOIC V NC 1 16 CC V INT RTCbat 2 15 X V out 3 14 CAP Top View X SO in 4 13 not to scale 12 SI WP 5 HOLD SCK 6 11 V 10 RTCcap 7 CS GND 9 HSB 8 Table 1. Pin Definitions Pin Name I/O Type Description CS Input Chip Select. Activates the device when pulled LOW. Driving this pin HIGH puts the device in low power standby mode. SCK Input Serial Clock. Runs at speeds up to a maximum of 25 MHz. All inputs are latched at the rising edge of
Inhaltszusammenfassung zur Seite Nr. 3
CY14B101P PRELIMINARY SRAM Read Device Operation A read cycle in CY14B101P is performed at the SPI bus speed CY14B101P is a 1-Mbit nvSRAM memory with integrated RTC and the data is read out with zero cycle delay after the READ and SPI interface. All the reads and writes to nvSRAM happen instruction is performed. The READ instruction is issued through to the SRAM which gives nvSRAM the unique capability to the SI pin of the nvSRAM and consists of the READ opcode and handle infinite writes to the
Inhaltszusammenfassung zur Seite Nr. 4
CY14B101P PRELIMINARY Figure 2. AutoStore Mode cycle is in progress. The RECALL operation in no way alters the data in the nonvolatile elements. Vcc Hardware Recall (Power Up) During power up, when V crosses V , an automatic CC SWITCH 0.1uF RECALL sequence is initiated which transfers the content of nonvolatile memory on to the SRAM. Vcc A Power Up Recall cycle takes t time to complete and the FA memory access is disabled during this time. HSB pin is used to detect the Ready status of the devic
Inhaltszusammenfassung zur Seite Nr. 5
CY14B101P PRELIMINARY master is the opcode. Following the opcode, any addresses and Data Transmission SI/SO data are then transferred. The CS must go inactive after an SPI data bus consists of two lines, SI and SO, for serial data operation is complete and before a new opcode can be issued. communication. The SI is also referred to as MOSI (Master Out The commonly used terms used in SPI protocol are given below: Slave In) and SO is referred to as MISO (Master In Slave Out). The master issues ins
Inhaltszusammenfassung zur Seite Nr. 6
CY14B101P PRELIMINARY Figure 3. System Configuration Using SPI nvSRAM SCK MOSI MISO SS C K SI SO CK S I SO uController C Y 1 4B 10 1 P C Y 1 4 B 1 0 1P CS HOLD CS HOLD CS1 HOLD1 CS2 HOLD2 The two SPI modes are shown in Figure 4 and Figure 5. The SPI Modes status of clock when the bus master is in Standby mode and not transferring data is: CY14B101P device may be driven by a microcontroller with its SPI peripheral running in either of the following two modes: ■ SCK remains at 0 for Mode 0 ■ SPI
Inhaltszusammenfassung zur Seite Nr. 7
CY14B101P PRELIMINARY Active Power and Standby Power Modes SPI Operating Features When Chip Select (CS) is LOW, the device is selected, and is in Power Up the Active Power mode. The device consumes I current, as CC Power up is defined as the condition when the power supply is specified in DC Electrical Characteristics on page 22. When Chip turned on and V crosses Vswitch voltage. During this time, the CC Select (CS) is HIGH, the device is deselected and the device Chip Select (CS) must be enabl
Inhaltszusammenfassung zur Seite Nr. 8
CY14B101P PRELIMINARY tion and read by RDSR instruction. However, only WPEN, BP1 Status Register and BP0 bits of the Status Register can be modified by using The status register bits are listed in Table 3. The status register WRSR instruction. WRSR instruction has no effect on WEN and consists of Ready bit (RDY) and data protection bits BP1, BP0, RDY bits. The default value shipped from the factory for BP1, WEN and WPEN. The RDY bit can be polled to check the BP2 and WPEN bits is ‘0’. Rea
Inhaltszusammenfassung zur Seite Nr. 9
CY14B101P PRELIMINARY Figure 7. Write Status Register (WRSR) Instruction Timing CS 0 1 2 3 4567 0 12345 67 SCK Data in Opcode SI 1 D7 0 0 0 D3 D2 0 0 0000 0 0 0 MSB LSB HI-Z SO by opcode for WRDI instruction. The WEN bit is cleared on the Write Protection and Block Protection rising edge of CS following a WRDI instruction. CY14B101P provides features for both software and hardware Figure 9. WRDI Instruction write protection using WRDI instruction and WP. Additionally, this device also provides
Inhaltszusammenfassung zur Seite Nr. 10
CY14B101P PRELIMINARY When WP pin is LOW and WPEN is set to “1”, any modifications data (D7-D0) at the specific address is shifted out on the SO line to status register are disabled. Therefore, the memory is on the falling edge of SCK. Any other data on SI line after the last protected by setting the BP0 and BP1 bits and the WP pin inhibits address bit is ignored. any modification of the status register bits, providing hardware CY14B101P allows reads to be performed in bursts through SPI write p
Inhaltszusammenfassung zur Seite Nr. 11
CY14B101P PRELIMINARY Figure 11. Burst Mode Read Instruction Timing CS 01 2 3 456 7 0 1 2 3 4 5 6 7 20 21 22 23 0123 4 5 67 0 0 1 234 567 7 SCK Op-Code 17-bit Address A16 SI 00 00 00 11 0 0 00 00 0 A3 A2 A1 A0 MSB LSB Data Byte N Data Byte 1 SO D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB MSB LSB Figure 12. Write Instruction Timing CS 0123 4 5 6 7 0 1 2 3 4 5 6 7 20 21 2223 01234567 SCK Op-Code 17-bit Address SI D7 D6 D5 D4 D3 D2 D1 D0 00 00 001 0 00 0 0 0 0 0 A16 A3 A2 A1 A0
Inhaltszusammenfassung zur Seite Nr. 12
CY14B101P PRELIMINARY Figure 14. Read RTC (RDRTC) Instruction Timing CS 0123 45 6 7 0 1 2 3 45 6 7 0123 45 6 7 SCK Op-Code 000 1 SI 001 1 00 0 0 A3 A2 A1 A0 MSB LSB SO D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB Data WRITE RTC (WRTC) Instruction of data. WRTC allows burst mode write operation. When writing more than one registers in burst mode, the address rolls over to WRITE RTC (WRTC) instruction allows the user to modify the 0x00 after the last RTC address (0x0F) is reached. contents of RTC registers.
Inhaltszusammenfassung zur Seite Nr. 13
CY14B101P PRELIMINARY bit is cleared on the positive edge of CS following the STORE bit is cleared on the positive edge of CS following the ASENB instruction. instruction. Software Recall (RECALL) Figure 19. AutoStore Enable Operation When a RECALL instruction is executed, CY14B101P performs CS a Software Recall operation. To issue this instruction, the device must be write enabled (WEN = ‘1’). 0 12 3 4 56 7 The instruction is performed by transmitting the RECALL opcode SCK on the SI pin fol
Inhaltszusammenfassung zur Seite Nr. 14
CY14B101P PRELIMINARY Backup Power Real Time Clock Operation The RTC in the CY14B101P is intended for permanently nvTIME Operation powered operation. The V or V pin is connected RTCcap RTCbat depending on whether a capacitor or battery is chosen for the The CY14B101P offers internal registers that contain clock, application. When the primary power, V , fails and drops below alarm, watchdog, interrupt, and control functions. The RTC CC V the device switches to the backup power supply. registers
Inhaltszusammenfassung zur Seite Nr. 15
CY14B101P PRELIMINARY The value of OSCF must be reset to ‘0’ when the time registers There are four alarm match fields - date, hours, minutes, and are written for the first time. This initializes the state of this bit seconds. Each of these fields has a match bit that is used to which may have become set when the system was first powered determine if the field is used in the alarm match logic. Setting the on. match bit to ‘0’ indicates that the corresponding field is used in the match process. D
Inhaltszusammenfassung zur Seite Nr. 16
CY14B101P PRELIMINARY . Interrupt register and can be used to drive level or pulse mode Figure 21. Watchdog Timer Block Diagram output from the INT pin. In pulse mode, the pulse width is internally fixed at approximately 200 ms. This mode is intended Clock to reset a host microcontroller. In the level mode, the pin goes to Oscillator 1 Hz Divider its active polarity until the Flags register is read by the user. This 32,768 KHz 32 Hz mode is used as an interrupt to a host microcontroller. The co
Inhaltszusammenfassung zur Seite Nr. 17
CY14B101P PRELIMINARY timekeeping registers to ensure that transitional values of time Accessing the Real Time Clock through SPI are not read. CY14B101P uses 16 registers for Real Time Clock (RTC). These Writes to the RTC register are performed using the WRTC registers can be read out or written to by accessing all 16 instruction. Writing RTC timekeeping registers and control registers in burst mode or accessing each register, one at a time. registers, except for the flag register needs the ‘W’
Inhaltszusammenfassung zur Seite Nr. 18
CY14B101P PRELIMINARY [1, 2] Table 9. RTC Register Map BCD Format Data Register Function/Range D7 D6 D5 D4 D3 D2 D1 D0 0x0F 10s Years Years Years: 00–99 0x0E 0 0 0 10s Months Months: 01–12 Months 0x0D 0 0 10s Day of Month Day Of Month Day of Month: 01–31 0x0C 0 0 0 0 0 Day of week Day of week: 01–07 0x0B 0 0 10s Hours Hours Hours: 00–23 0x0A 0 10s Minutes Minutes Minutes: 00–59 0x09 0 10s Seconds Seconds Seconds: 00–59 [3] 0x08 OSCEN 0Cal Sign Calibration (00000) Calibration Values (0) (0) [3]
Inhaltszusammenfassung zur Seite Nr. 19
CY14B101P PRELIMINARY Table 10. Register Map Detail Time Keeping - Years D7 D6 D5 D4 D3 D2 D1 D0 0x0F 10s Years Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99. Time Keeping - Months D7 D6 D5 D4 D3 D2 D1 D0 0x0E 0 0 0 10s Month Months Contains the BCD digits of the month. Lower nibble (four bits) contains
Inhaltszusammenfassung zur Seite Nr. 20
CY14B101P PRELIMINARY Table 10. Register Map Detail (continued) WatchDog Timer 0x07 D7 D6 D5 D4 D3 D2 D1 D0 WDS WDW WDT WDS Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0. WDW Watchdog Write Enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value (D5–D0). This enables the user to
