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User’s Manual
78K/0 Series
Instructions
Common to 78K/0 Series
Document No. U12326EJ4V0UM00 (4th edition)
Date Published October 2001 N CP(K)
© 1995
Printed in Japan
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[MEMO] User's Manual U12326EJ4V0UM 2
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build stati
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The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is current as of August, 2001. The information is subject to change without notice. For actual design-i
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools
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Major Revisions in This Edition Page Description Throughout Deletion of all information except for information common to the 78K/0 Series (for individual product information, refer to the user’s manual of each product). The mark shows major revised points. User's Manual U12326EJ4V0UM 6
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INTRODUCTION Target Readers This manual is intended for users who wish to understand the functions of 78K/0 Series products and to design and develop its application systems and programs. Purpose This manual is intended to give users an understanding of the various kinds of instruction functions of 78K/0 Series products. Organization This manual is broadly divided into the following sections. • CPU functions • Instruction set • Explanation of instructions How to Read This Manual It is assumed th
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Documents Common to 78K/0 Series Document Name Document No. User’s Manual Instructions This manual Note Application Note Basic I U12704E Basic II U10121E Basic III U10182E Note Some subseries may not be covered. Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each d
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CONTENTS CHAPTER 1 MEMORY SPACE ...............................................................................................................12 1.1 Memory Spaces ................................................................................................................12 1.2 Internal Program Memory (Internal ROM) Space ..........................................................12 1.3 Vector Table Area ........................................................................................
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS .................................................................................46 5.1 8-Bit Data Transfer Instructions......................................................................................48 5.2 16-Bit Data Transfer Instructions....................................................................................51 5.3 8-Bit Operation Instructions ............................................................................................54
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LIST OF FIGURES Figure No. Title Page 2-1 Program Counter Configuration.............................................................................................................. 14 2-2 Program Status Word Configuration....................................................................................................... 14 2-3 Stack Pointer Configuration .................................................................................................................... 16 2-4 Data to Be Save
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CHAPTER 1 MEMORY SPACE 1.1 Memory Spaces The 78K/0 Series product program memory map varies depending on the internal memory capacity. For details of memory-mapped address area, refer to the user’s manual of each product. 1.2 Internal Program Memory (Internal ROM) Space Each 78K/0 Series product has internal ROM in the address space. Program and table data, etc. are stored in the ROM. Normally, this memory space is addressed by the program counter (PC). For details of the internal ROM s
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CHAPTER 1 MEMORY SPACE (3) RAM for VFD display There are some products in the 78K/0 Series to which RAM for VFD display is allocated. This RAM can also be used as an ordinary RAM area. (4) Internal expansion RAM There are some products in the 78K/0 Series to which internal expansion RAM is allocated. (5) RAM for LCD display There are some products in the 78K/0 Series to which RAM for LCD display is allocated. This RAM can also be used as an ordinary RAM area. 1.7 Special Function Register (S
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CHAPTER 2 REGISTERS 2.1 Control Registers The control registers control the program sequence, statuses and stack memory. A program counter, a program status word and a stack pointer are the control registers. 2.1.1 Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instructi
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CHAPTER 2 REGISTERS (1) Interrupt enable flag (IE) This flag controls the interrupt request acknowledgement operations of the CPU. When IE = 0, the IE flag is set to interrupt disable (DI), and interrupts other than non-maskable interrupts are all disabled. When IE = 1, the IE flag is set to interrupt enable (EI), and interrupt request acknowledgement is controlled by an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag. This
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CHAPTER 2 REGISTERS 2.1.3 Stack pointer (SP) This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 2-3. Stack Pointer Configuration 15 0 SP The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. Each stack operation saves/resets data as shown in Figures 2-4 and 2-5. Caution Since RESET input makes SP contents undefined, be
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CHAPTER 2 REGISTERS 2.2 General-Purpose Registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. These registers consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16- bit register (AX, BC, DE and HL). General-purpose registers can be described in terms of functional names (X, A, C, B, E, D
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CHAPTER 2 REGISTERS Figure 2-6. General-Purpose Register Configuration (a) Absolute names 16-bit processing 8-bit processing FEFFH R7 BANK0 RP3 R6 FEF8H FEF7H R5 BANK1 RP2 R4 FEF0H FEEFH R3 BANK2 RP1 R2 FEE8H FEE7H R1 BANK3 RP0 R0 FEE0H 15 0 7 0 (b) Functional names 16-bit processing 8-bit processing FEFFH H BANK0 HL L FEF8H FEF7H D BANK1 DE E FEF0H FEEFH B BANK2 BC C FEE8H FEE7H A BANK3 AX X FEE0H 15 0 7 0 18 User's Manual U12326EJ4V0UM
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CHAPTER 2 REGISTERS 2.3 Special Function Registers (SFRs) Unlike a general-purpose register, each special-function register has a special function. Special function registers are allocated in the 256-byte area FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, by operation, transfer and bit manipulation instructions. The manipulatable bit units (1, 8, and 16) differ depending on the special function register type. Each manipulation bit unit can be s
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CHAPTER 3 ADDRESSING 3.1 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of each instruction, refer to CHAPTER 5 EXP
