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TMS320C645x DSP
General-Purpose Input/Output (GPIO)
User’s Guide
Literature Number: SPRU724
December 2005
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Preface Read This First About This Manual This document describes the general-purpose input/output (GPIO) peripheral in the digital signal processors (DSPs) of the TMS320C645x™ DSP family. Notational Conventions This document uses the following conventions. Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. When referencing specific register bits, the X in the register bit name is replaced with the bit number; for example,
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Trademarks Related Documentation From Texas Instruments / Trademarks TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and assembly code for the TMS320C6000 DSPs and includes application program examples. TMS320C6000 Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studio integrated develop- ment environment and software tools. Code Composer Studio Application Programming Interface Reference Guide (literature number SP
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Contents Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 GPIO Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Interrupt and Event Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Emulation Halt Operation .
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Figures Figures 1 TMS320C645x DSP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 GPIO Peripheral Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Interrupt Per-Bank Enable Register (BINTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Direction Register (DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Tables Tables 1 GPIO Interrupt and EDMA Event Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions . . . . . . . . . . . . . . . . . . . . . 16 4 Direction Register (DIR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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General-PurposeInput/Output(GPIO) This document describes the general-purpose input/output (GPIO) peripheral in the digital signal processors (DSPs) of the TMS320C645x™ DSP family. 1 Overview The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an output, you can write to an internal register to control the state driven on the output pin. When configured as an input, you can detect the
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Overview Figure 1. TMS320C645x DSP Block Diagram L1P cache/SRAM EMIFA L2 memory L1 program memory controller Advanced controller event Cache control triggering Bandwidth management (AET) Cache DDR2 memory control Memory protection controller Bandwidth management C64x+ CPU Memory Instruction fetch PLL2 IDMA protection SPLOOP buffer 16/32−bit instruction dispatch Instruction decode Data path A Data path B GPIO External memory L1 S1 M1 D1 D2 M2 S2 L2 controller Configuration Register file A Registe
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Overview Figure 2. GPIO Peripheral Block Diagram GPIO peripheral Data input/output Direction DIR Set SET_DATA data Output † GPn OUT_DATA data Peripheral clock Clear (CPU/6) CLR_DATA data Input Synchronization IN_DATA data logic EDMA event and interrupt Interrupt and generation Edge detection EDMA event logic ‡ (GPINTn ) Set rising SET_RIS_TRIG edge trigger Rising edge § RIS_TRIG trigger Clear rising CLR_RIS_TRIG edge trigger Set falling SET_FAL_TRIG edge trigger Falling edge § FAL_TRIG trigger C
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GPIO Function 2 GPIO Function You can independently configure each GPIO pin (GPn) as either an input or an output using the GPIO direction registers. The GPIO direction register (DIR) specifies the direction of each GPIO signal. Logic 0 indicates the GPIO pin is configured as output, and logic 1 indicates input. When configured as output, writing a 1 to a bit in the set data register drives the corresponding GPn to a logic-high state. Writing a 1 to a bit in the clear data register drives the co
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Interrupt and Event Generation 3 Interrupt and Event Generation Each GPIO pin (GPn) can be configured to generate a CPU interrupt (GPINTn) and a synchronization event to the EDMA controller (GPINTn). The interrupt and EDMA event can be generated on the rising-edge, falling-edge, or on both edges of the GPIO signal. The edge detection logic is synchronized to the GPIO peripheral clock. The direction of the GPIO pin does not need to be input when using the pin to generate the interrupt and EDMA ev
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Emulation Halt Operation Interrupt and Event Generation / Interrupts and Events Reading the SET_RIS_TRIG or CLR_RIS_TRIG register returns the value of RIS_TRIG register. Reading from SET_FAL_TRIG and CLR_FAL_TRIG register returns the value of FAL_TRIG register. To use the GPIO pins as sources for CPU interrupts and EDMA events, bit 0 in the bank interrupt enable register (BINTEN) must be set to 1. 4 Emulation Halt Operation The GPIO peripheral is not affected by emulation halts. 14 General-Purpo
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Registers 5 Registers The GPIO peripheral is configured through the registers listed in Table 2. See the device-specific datasheet for the memory address of these registers. Table 2. GPIO Registers Offsets Acronym Register Name Section 0008 BINTEN Interrupt Per-Bank Enable Register 5.1 0010 DIR Direction Register 5.2 0014 OUT_DATA Output Data Register 5.3 0018 SET_DATA Set Data Register 5.4 001C CLR_DATA Clear Data Register 5.5 0020 IN_DATA Input Data Register 5.6 0024 SET_RIS_TRIG Set Rising Ed
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Registers 5.1 Interrupt Per-Bank Enable Register (BINTEN) To use the GPIO pins as sources for CPU interrupts and EDMA events, bit 0 in the bank interrupt enable register (BINTEN) must be set. BINTEN is shown in Figure 3 and described in Table 3. Figure 3. Interrupt Per-Bank Enable Register (BINTEN) 31 10 Reserved EN R-0 RW-0 Legend: R = Read only; R/W = Read/Write; -n = value after reset Table 3. Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions Bit Field Value Description 31−1 Rese
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Registers 5.2 Direction Register (DIR) The GPIO direction register (DIR) determines if a given GPIO pin is an input or an output. The GPDIR is shown in Figure 4 and described in Table 4. By default, all the GPIO pins are configured as input pins. When GPIO pins are configured as output pins, the GPIO output buffer drives the GPIO pin. If it is necessary to place the GPIO output buffer in a high-impedance state, the GPIO pin must be configured as an input pin (DIRn = 0). At reset, GPIO pins defau
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Registers 5.3 Output Data Register (OUT_DATA) The GPIO output data register (OUT_DATA) indicates the value to be driven on a given GPIO output pin. The OUT_DATA registers are shown in Figure 5 and described in Table 5. Figure 5. Output Data Register (OUT_DATA) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7654 3210 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Legend
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Registers 5.4 Set Data Register (SET_DATA) The GPIO set data register (SET_DATA) is shown in Figure 6 and described in Table 6. SET_DATA provides an alternate means of driving GPIO outputs high. Writing a 1 to a bit of SET_DATA sets the corresponding bit in OUT_DATA. Writing a 0 has no effect. Reading SET_DATA returns the contents of OUT_DATA. Figure 6. Set Data Register (SET_DATA) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 SET15 SET14 SET13 SET12 SET11 SET10 SET9 SET8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-
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Registers 5.5 Clear Data Register (CLR_DATA) The GPIO clear data register (CLR_DATA) is shown in Figure 7 and described in Table 7. CLR_DATA provides an alternate means of driving GPIO outputs low. Writing a 1 to a bit of CLR_DATA clears the corresponding bit in OUT_DATA. Writing a 0 has no effect. Reading CLR_DATA returns the contents of OUT_DATA. Figure 7. Clear Data Register (CLR_DATA) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 CLR15 CLR14 CLR13 CLR12 CLR11 CLR10 CLR9 CLR8 R/W-0 R/W-0 R/W-0 R/W
