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PLB PCI Full Bridge (v1.00a)
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DS508 March 21, 2006 Product Specification
Introduction
LogiCORE™ Facts
The PLB PCI Full Bridge design provides full bridge
Core Specifics
functionality between the Xilinx 64-bit PLB and a 32-bit
Supported Device
Virtex™-II Pro, Virtex-4
Revision 2.2 compliant Peripheral Component
Family
Interconnect (PCI) bus. The bridge is referred to as the
Version of Core plb_pci v1.00a
PLB PCI Bridge in this document.
Resources Used
The Xilinx PLB is a 64-bit bus subs
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PLB PCI Full Bridge (v1.00a) Features • Independent PLB and PCI clocks 33 MHz, 32-bit PCI bus support Utilizes two pairs of FIFOs to exploit the separate master and slave PLB IPIF modules. Includes a master IP module for remote PCI initiator transactions, which follows the protocol for interfacing with the master IPIF module utilizing Xilinx LocalLink protocol. The PLB PCI Bridge translates the PCI initiator request to PLB IPIF master transactions. Includes a slave IP module for remote
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PLB PCI Full Bridge (v1.00a) default in all transfers. Address translation is performed by high-order bit substitution. High-order bit definition is defined only by parameters Registers include - Interrupt and interrupt enable registers at different hierarchal levels -Reset - Configuration Address Port, Configuration Data Port and Bus Number/Subordinate Bus Number - High-order bits for PLB to PCI address translation - Bridge Device number on PCI bus PLB-side Interrupts include - PLB Master
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PLB PCI Full Bridge (v1.00a) System Reset When the bridge is reset, both RST_N and PLB_reset must be simultaneously held at reset for at least twenty clock periods of the slowest clock. Evaluation Version The PLB PCI Bridge is delivered with a hardware evaluation license. When programmed into a Xilinx device, the core will function in hardware for about 8 hours at the typical frequency of operation. To use the PLB PCI Bridge without this timeout limitation, a full license must be purchased. F
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PLB PCI Full Bridge (v1.00a) core. These documents detail the v3.0 core operation, including configuration cycles, and are available from Xilinx. As required by the LogiCORE v3.0 core, GNT_N must be asserted for two clock cycles to initiate a PCI transaction by the PLB PCI Bridge. Bus Interface Parameters Because many features in the IPIF v3.0 Bridge design can be parameterized, the user can realize a PLB PCI Full Bridge uniquely tailored while using only the resources required for the desire
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BAR_11 PLB PCI Full Bridge (v1.00a) Example 3 outlines the use of the PCIBAR parameter sets for the address translation of PCI addresses within the range of a given PCIBAR to a remote PLB address space. Figure Top x-ref 2 BAR_10 PLB Bus PLB PCI Full Bridge IPIF C_IPIFBAR_NUM = 3 IPIFBAR_0 IPIFBAR_1 IPIFBAR_2 IPIFBAR_3 IPIFBAR_4 IPIFBAR_5 Note 1 (high-order (high-order (high-order IPIF to v3.0 LogiCORE Bridge bit sub) bit sub) bit sub) Addr to PCI Addr to PCI Addr to PCI Addr to PLB Addr to PLB
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PLB PCI Full Bridge (v1.00a) As in example 1, it is assumed that the parameter C_INCLUDE_BAROFFSET_REG=0, therefore the C_IPIFBAR2PCIBAR_N parameters define the address translation. In this example, where C_IPIFBAR_NUM=4, the following assignments for each range are made: C_IPIFBAR_0=0x12340000 C_IPIF_HIGHADDR_0=0x1234FFFF C_IPIFBAR2PCIBAR_0=0x5671XXXX (Bits 16-31 are don’t cares) C_IPIFBAR_1=0xABCDE000 C_IPIF_HIGHADDR_1=0xABCDFFFF C_IPIFBAR2PCIBAR_1=0xFEDC0xXX (Bits 19-31 are don’t cares) C_I
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PLB PCI Full Bridge (v1.00a) Accessing the PLB PCI Bridge PCIBAR_1 with address 0x1235FEDC on the PCI bus yields 0xFE35FEDC on the PLB bus. Table 1: PLB PCI Bridge Interface Design Parameters Feature / Parameter Default VHDL Generic Allowable Values Description Name Value Type Bridge Features Parameter Group 1-6; Parameters listed below corresponding to unused BARs are ignored, but must be C_IPIFBAR G1 Number of IPIF devices 6 integer valid values. BAR label _NUM 0 is the required ba
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PLB PCI Full Bridge (v1.00a) Table 1: PLB PCI Bridge Interface Design Parameters (Contd) Feature / Parameter Default VHDL Generic Allowable Values Description Name Value Type IPIF BAR 2 memory C_IPIF_SPACE 0 = I/O space G13 1 integer designator TYPE_2 1 = Memory space std_logic_ (1), (2) G14 IPIF device 3 BAR C_IPIFBAR_3 Valid PLB address 0xFFFFFFFF vector IPIF BAR high C_IPIFBAR_ std_logic_ (1), (2) G15 Valid PLB address 0x00000000 address 3 HIGHADDR_3 vector PCI BAR to which IPIF BAR 3 is
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PLB PCI Full Bridge (v1.00a) Table 1: PLB PCI Bridge Interface Design Parameters (Contd) Feature / Parameter Default VHDL Generic Allowable Values Description Name Value Type IPIF BAR to which PCI C_PCIBAR2 Vector of length std_logic_ G27 BAR 0 0x00000000 IPIFBAR_0 C_PLB_AWIDTH vector is mapped Power of 2 in the size in C_PCIBAR_ G28 bytes of PCI BAR 0 5 to 29 16 integer LEN_0 space IPIF BAR to which PCI C_PCIBAR2IPI Vector of length std_logic_ G29 0x00000000 BAR 1 is mapped FBAR_1 C_PLB_
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PLB PCI Full Bridge (v1.00a) Table 1: PLB PCI Bridge Interface Design Parameters (Contd) Feature / Parameter Default VHDL Generic Allowable Values Description Name Value Type PCI2IPIF FIFO 2 to the lesser of 24 or occupancy level in the PCI2IPIF FIFO double words that C_TRIG_IPIF_ DEPTH-3. PCI2IPIF G40 WRBURST_ 8 integer triggers the bridge to FIFO DEPTH given by initiate an IPIF burst OCC_LEVEL 2^C_PCI2IPIF_FIFO_A write to remote PLB BUS_WIDTH device IPIF2PCI FIFO occupancy level t
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PLB PCI Full Bridge (v1.00a) Table 1: PLB PCI Bridge Interface Design Parameters (Contd) Feature / Parameter Default VHDL Generic Allowable Values Description Name Value Type Number of IDELAY 2-6 C_NUM_ G50 controllers instantiated. 2 integer IDELAYCTRL (Virtex-4 only) Ignored it not Virtex-4 1=Include IDELAY Includes IDELAY primitive primitive on GNT_N. C_INCLUDE_ G51 0 integer Set by tcl-scripts and GNT_DELAY (Virtex-4 only) ignored if not Virtex-4. 0=No IDELAY primitive Provides a mea
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PLB PCI Full Bridge (v1.00a) Table 1: PLB PCI Bridge Interface Design Parameters (Contd) Feature / Parameter Default VHDL Generic Allowable Values Description Name Value Type Include configuration C_INCLUDE_ 0 = Not included G61 functionality via IPIF 1 integer PCI_CONFIG 1 = Included transactions Number of IDSEL C_NUM_ G62 1 to 16 8 integer signals supported IDSEL 31 down to 16 PCI address bit that PCI C_BRIDGE_ Must be <= 15 + G63 v3.0 core IDSEL is IDSEL_ADDR_ C_NUM_IDSEL. 16 integer BI
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PLB PCI Full Bridge (v1.00a) PLB PCI Bus Interface I/O Signals The I/O signals for the PLB PCI Bridge are listed in Table 2. The interfaces referenced in this table are shown in Figure 1 in the PLB PCI Bridge block diagram. Table 2: PLB PCI Bridge I/O Signals Port Signal Name Interface I/O Description System Signals P1 IP2INTC_Irpt Internal O Interrupt from IP to the Interrupt Controller PLB Signals P2 PLB_Clk PLB Bus I PLB main bus clock. See table note 1. P3 PLB_Rst PLB Bus I PLB main bus
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PLB PCI Full Bridge (v1.00a) Table 2: PLB PCI Bridge I/O Signals (Contd) Port Signal Name Interface I/O Description P27 Sl_rdBTerm PLB Bus O Sl_MBusy(0:C_PLB_NU P28 PLB Bus O M_MASTERS-1) Sl_MErr(0:C_PLB_NUM P29 PLB Bus O _MASTERS-1) P30 PLB_MAddrAck PLB Bus I P31 PLB_MSSize(0:1) PLB Bus I P32 PLB_MRearbitrate PLB Bus I P33 PLB_MBusy PLB Bus I P34 PLB_MErr PLB Bus I P35 PLB_MWrDAck PLB Bus I PLB_MRdDBus(0:C_PL P36 PLB Bus I B_DWIDTH-1) P37 PLB_MRdWdAddr(0:3) PLB Bus I P38 PLB_MRdDAck PLB Bus
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PLB PCI Full Bridge (v1.00a) Table 2: PLB PCI Bridge I/O Signals (Contd) Port Signal Name Interface I/O Description CBE[(C_PCI_DBUS_WI P55 PCI Bus I/O Time-multiplexed bus command and byte enable bus DTH/8)-1:0] Generates and checks even parity across AD and P56 PAR PCI Bus I/O CBE PCI Transaction Control Signals P57 FRAME_N PCI Bus I/O Driven by an initiator to indicate a bus transaction Indicates that a target has decoded the address P58 DEVSEL_N PCI Bus I/O presented during the address p
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PLB PCI Full Bridge (v1.00a) Table 2: PLB PCI Bridge I/O Signals (Contd) Port Signal Name Interface I/O Description Input from PCI Bus IRDY_N availalble at top-level as P72 IRDY_I Internal O output from bridge PCI 64-bit Extensions (reserved for future support of 64-bit PCI) Generates and checks even parity across AD[63:32] P73 PAR64 PCI Bus I/O and CBE[7:4] Indicates that a target has decoded the address P74 ACK64_N PCI Bus I/O presented during the address phase and is claiming the trans
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PLB PCI Full Bridge (v1.00a) Port and Parameter Dependencies The dependencies between the IPI v3.0 Bridge design port (i.e., I/O signals) and parameters are shown in Table 1. Table 3: PLB PCI Bridge Parameters-Port Dependencies Generic Parameter Affects Depends Description Bridge Features Parameter Group The set of PLB/IPIF BAR-parameters of N = 0 to C_IPIFBAR_NUM-1 are meaningful. When C_IPIFBAR_NUM < 6, the parameters of N = G1 C_IPIFBAR_NUM G5-G25 C_IPIFBAR_NUM up to and including 5
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PLB PCI Full Bridge (v1.00a) Table 3: PLB PCI Bridge Parameters-Port Dependencies (Contd) Generic Parameter Affects Depends Description G1, G10, Meaningful only if G48 = 0 and G1>2. In G12 C_IPIFBAR2PCIBAR_2 G11 and this case only high-order bits that are the G48 same in G10 and G11 are meaningful. G13 C_IPIF_SPACETYPE_2 G1 Meaningful only if G1>2 Meaningful only if G1>3, then G14 to G1 and G15 define the range in PLB-memory G14 C_IPIFBAR_3 G15 G15 space that is responded to by this devic
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PLB PCI Full Bridge (v1.00a) Table 3: PLB PCI Bridge Parameters-Port Dependencies (Contd) Generic Parameter Affects Depends Description The set of PCI/v3.0 BAR-parameters of N = 0 to C_PCIBAR_NUM-1 are meaningful and the parameters of N = C_PCIBAR_NUM up to and including 2 G26 C_PCIBAR_NUM G27-G32 have no effect. If C_PCIBAR_NUM = 3, the set of PCI/v3.0 BAR-parameters of N = 0 to 2 are all meaningful (i.e., G27-G32 are meaningful) Only the high-order bits above the length G27 C_PCIBAR
