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ATA6264 [Preliminary] 3. Absolute Maximum Ratings (Continued) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to an ideal gro
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4. Functional Range Within the functional range, the ATA6264 works as specified. All voltages are referenced to the ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins. At the beginning of each specification table, supply voltage and temperature conditions are described. Table 4-1. Electrical Characteristics – Functional Range No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Voltage on pins K30, K15, 1.1 –0.3 +40 V USP 1.1a Voltage on pins K1, K2 –25 +40 V
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ATA6264 [Preliminary] 4.1 Protection Against Substrate Currents Due to the fact that the ATA6264 is connected to the wiring harness and to components outside of the ECU, negative voltages at the following pins might occur: IASG interface: IASG1, IASG2, IASG3, IASG4, IASG5 USP comparator: USP If substrate currents occur, it is guaranteed by design that no disturbance and malfunction of the following blocks and functions will happen: No disturbance of RESET block. No voltage changes of any
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5. Supply Currents A minimum current has to flow into each pin for proper functioning of the IC. Table 5-1. Electrical Characteristics – Supply currents No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Standby mode: 0V = V = 18V, K30 2.1 Supply current at K30 K30 I 050µAA K30 V = 3V and KEYLATCH = OFF K15 Standby mode: 18V < V = 40V, K30 2.1a Supply current at K30 K30 I 05mAA K30 V = 3V and KEYLATCH = OFF K15 Startup mode: 0V < V = 18V, K30 2.1b Supply current at K30 V > 4.
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ATA6264 [Preliminary] 5.1 Discharger Circuit Applications using the ATA6264 usually use a reverse polarity protection diode (D1 in Figure 5-1) in the power supply to prevent any damage if the wrong polarity is applied to V . Unfortu- K30 nately, this method includes some risk as can be seen in the following description: During Standby mode (V < 3V and KEYLATCH = OFF) the IC consumes only a low current, K15 I . Any peaks on the supply voltage (V in Figure 5-1) will gradually charge the blocking K
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The following settings can be made at the initial programming: MSBit LSBit VR1 VR2 VR3 VR4 EXT ISO/LIN Parity Lock bit Table 5-2. Initial Programming Settings VR1 VR2 VR3 VR4 VCORE VPERI VSAT 0 0 0 0 All regulators deactivated (default) 0 0 0 1 1.88V 3.3V 7.8V 0 0 1 0 1.88V 3.3V 9.1V 0 0 1 1 1.88V 3.3V 10.4V 0 1 0 0 2.5V 3.3V 7.8V 0 1 0 1 2.5V 3.3V 9.1V 0 1 1 0 2.5V 3.3V 10.4V 0 1 1 1 1.88V 5V 7.8V 1 0 0 0 1.88V 5V 9.1V 1 0 0 1 1.88V 5V 10.4V 1 0 1 0 2.5V 5V 7.8V 1 0 1 1 2.5V 5V 9.1V 1 1 0 0 2.5
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ATA6264 [Preliminary] The IP data is valid only if the parity is odd. If the IP data is not valid, or if the lock bit is not set, the programming will not be executed. Figure 5-2. Programming Sequence Contact pins RESQ, RESQ2 TxD1, TxD2, SSQ, MOSI, SCLK, VPERI, K15, K30 Apply 12V at K15, K30 and5V at VPERI Set RESQ and TxD1 to GND and RESQ2 and TxD2 to 5V Transmit 5A5A(h) via SPI to Enable Testmode Wait until VSAT = 11.7V Transmit IP command A9xx(h) via SPI to configure ATA6264 Wait 1 ms Remove
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5.3 Start-up and Power-down Procedure The ATA6264 is powered via the pin K30 (battery voltage) and via a diode or a resistor it is con- nected to the ignition key line K15. In order to detect an interruption on one of these pins correctly, resistors are implemented at these pins. Normally, the main supply pin of ATA6264 is pin K30. In the case of a missing or a too-low voltage at pin K30, the whole IC is supplied from the backup power supply capacitor hooked up to pin EVZ. Figure 5-3. Block Diag
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ATA6264 [Preliminary] Depending on the initial programming of the ATA6264, the start-up procedure takes place in dif- ferent phases. 5.3.1 Start-up Procedure if V is Programmed to Be 5V or 2.5V VCORE Phase1: After switching on the ignition key, K15 voltage will apply at pin K15. If, in addition, the voltage at pin K30 is larger than 3.85V to 5V, the EVZ regulator will be enabled. The signal K15GOOD can be replaced by the serial interface command KEYLATCH which can be set via the serial interfac
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Figure 5-4. Start-Up and Power-Down Procedure if V Programmed to Be 5V or 2.5V VCORE V K30 t V K15 3V to 4.15V 3V to 4.15V t V GEVZ Threshold to enable t VCORE regulator V EVZ 7.5V to 9V too low EVZ voltage 5.5V to 6.2V VSAT goes into On Mode charge pump deactivated Threshold to start t VCORE regulator V VSAT 6.77V to 7.2V 7V to 6.27V t V VPERI t V VCORE t 5.3.3 Start-up Procedure if V Programmed to Be 1.88V VCORE Phase1: After switching on the ignition key, the K15 voltage will appear at pi
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ATA6264 [Preliminary] 5.3.4 The Power-down Procedure for V is Programmed to be 1.88V VCORE Phase1: If the ignition key is switched off, the K15 voltage will vanish at pin K15. If the serial interface command KEYLATCH is not set, the EVZ regulator stops working. The external charge pump is still working because EVZ is above VSAT and the VSAT regulator is not in the Perma- nent-on mode. The charge-pump voltage still supplies the VSAT regulator and the VCORE regulator. Because the EVZ regulator sto
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6. Power Supply Sequencing (Only active when initial programming sets V = 1.88V and V = 3.3V) VCORE VPERI In order to meet the requirements of several dual-voltage-supply microcontrollers, a power-sequencing function is implemented. The ATA6264 ensures that the voltage difference VPERI – VCORE will not exceed 2.8V. The voltage difference between VPERI and VCORE is monitored. In error cases, for example, if the VCORE regulator does not start to work, the difference may rise above the 2.8V thresh
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ATA6264 [Preliminary] Figure 6-2. Block Diagram Power Supply Sequencing K15 K15GOOD VEVZ V = 3V to 4.15V K15 Comp (40 mV to 175mV Hysteresis) K30 Serial interface (KEY - LATCH) V CP CP IREF lost signal K30GOOD VK30 V = 3.85V to 5V K30 EVZEN GEVZ Comp (50 mV to 150 mV Hysteresis) VEVZ driver CORESWAP V = 6.1V to 8.1V (ON) K30 5V Comp (0.5V to 1V Hysteresis) IP V EVZ EVZ VCP V = 7.5V to 9V (ON) EVZ EVZGOOD V = 5.5V to 6.2V (OFF) EVZ Comp VSAT SVSAT driver V VSAT VSAT VEVZ VSATGOOD V = 6.77V to 7.
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7. Charge Pump (1) To supply the VSAT and VCORE drivers, an external charge pump is provided. Both FETs are driven by the high charge pump voltage V to ensure that they can be switched to a low-ohmic CP state. For correct function of the charge pump, an external capacitor of C = 47 nF has to be con- nected to pin SVSAT, and another of C = 100 nF to pin CP. A double diode has to be implemented for proper function of the charge pump. An external series resistor is recom- mended to suppress spikes
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Features
• Maximum Supply Voltage 40V
One Programmable/Adjustable Boost Converter
Two Programmable Buck Converters
One Programmable Linear Regulator
OTP Customer Mode
16-bit Serial Interface
Two ISO9141 Interfaces (One Interface Programmable to LIN Functionality)
Watchdog
Airbag Power
Various Diagnosis Functions
5 Voltage Sources Tailored to Resistor Measurement
Supply IC
Charge Pump
Small, 44-pin Package
ESD Protection Against 2kV and 4kV
ATA6264
1. Description
®
With
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Figure 1-1. Block Diagram SVSAT V BATT VSAT RESQ Serial Interface K30 GKEY- CP Logic Watchdog Logic RESQ2 Reset GNDD GEVZ OCEVZ EVZ- TxD1 Regulator GNDB RxD1 V TxD2 EVZ EVZ RxD2 FBEVZ K1 ISO9141 K2 COMEVZO SVSAT COMSATO IASG1 IASG2 VSAT- Regulator IASG3 COMSATI IASG IASG4 V VSAT VSAT IASG5 SVPERI ISENS VPERI- V VPERI Regulator VPERI SVCORE UZP UZP AMUX VCORE V VCORE GNDA COMCOI VCORE- Internal Supply USP Regulator Reference COMCOO V BATT 2 ATA6264 [Preliminary] 4929B–AUTO–01/07 MOSI MISO SSQ U
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ATA6264 [Preliminary] 1.1 Block Description 1.1.1 Integrated Boost Converter EVZ With an external n-channel FET, the integrated boost converter EVZ provides 3 different volt- ages adjustable via the serial interface for the energy reserve and firing capacitors. Two voltages are fixed values; one voltage can be adjusted using an external resistive divider. 1.1.2 Integrated Buck Converter VSAT The integrated buck converter VSAT is a fully integrated step-down converter supplied by the boost conver
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2. Pin Configuration Figure 2-1. Pinning QFP44 44 43 42 41 40 39 38 37 36 35 34 USP 1 33 K15 K30 2 32 EVZ K1 SVSAT 3 31 K2 4 30 VSAT IASG1 5 29 GNDD IASG2 6 28 VINT IASG3 7 27 COMSATI IASG4 8 26 VCORE IASG5 9 25 GNDA ISENS 10 24 SVPERI TxD1 11 23 VPERI 12 13 14 15 16 17 18 19 20 21 22 Table 2-1. Pin Description Pin Symbol Function 1 USP Comparator input 2 K30 Continuous connection to the car battery st 3 K1 Bus line of 1 ISO9141 interface nd 4 K2 Bus line of 2 ISO9141 interface 5 IASG1 Output
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ATA6264 [Preliminary] Table 2-1. Pin Description Pin Symbol Function 23 VPERI Input for the VPERI regulator, internally used VPERI supply 24 SVPERI Output of VPERI regulator power transistor 25 GNDA Analog GND 26 VCORE Input for VCORE regulator 27 COMSATI Input of the VSAT externally compensated error amplifier 28 VINT Output of internal supply voltage 29 GNDD Digital GND 30 VSAT Input for VSAT regulator, internally used VSAT supply 31 SVSAT Output of VSAT regulator power transistor 32 EVZ Input
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3. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to an ideal ground level of an ECU connected to t
