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CY7C1352G
4-Mbit (256K x 18) Pipelined SRAM with
NoBL™ Architecture
[1]
Features Functional Description
• Pin compatible and functionally equivalent to ZBT™ The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined
devices Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
• Internally self-timed output buffer control to eliminate
wait states. The CY7C1352G is equipped with the advanced
the need to use OE
No Bus Latency™ (NoBL™)
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CY7C1352G Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz Unit Maximum Access Time 2.6 2.8 3.5 4.0 ns Maximum Operating Current 325 265 240 225 mA Maximum CMOS Standby Current 40 40 40 40 mA Pin Configuration 100-Pin TQFP Pinout 1 NC 80 A 2 NC 79 NC 3 NC 78 NC V 4 77 DDQ V DDQ V 5 76 SS V SS NC 6 75 NC NC 7 74 DQP A DQ 8 B 73 DQ A DQ 9 B 72 DQ A V 10 SS 71 V SS V DDQ 11 70 V DDQ DQ 12 69 B DQ A CY7C1352G DQ 13 B 68 DQ A NC 14 67 V BYTE A SS 15 BYTE B V NC DD 66 NC 16 65 V DD 17 V ZZ 64 SS D
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CY7C1352G Pin Definitions Name I/O Description A0, A1, A Input- Address Inputs used to select one of the 256K address locations. Sampled at the rising Synchronous edge of the CLK. A are fed to the two-bit burst counter. [1:0] BW Input- Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled [A:B] Synchronous on the rising edge of CLK. WE Input- Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. Synchronous This signal must
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CY7C1352G the state of chip enables inputs or WE. WE is latched at the Functional Overview beginning of a burst cycle. Therefore, the type of access (Read The CY7C1352G is a synchronous-pipelined Burst SRAM or Write) is maintained throughout the burst sequence. designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through Single Write Accesses input registers controlled by the rising edge of the clock. The Write accesses are initiated when the
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CY7C1352G Interleaved Burst Address Table Linear Burst Address Table (MODE = GND) (MODE = Floating or V ) DD First Second Third Fourth Address Address Address Address First Second Third Fourth A1, A0 A1, A0 A1, A0 A1, A0 Address Address Address Address A1, A0 A1, A0 A1, A0 A1, A0 00 01 10 11 00 01 10 11 01 10 11 00 01 00 11 10 10 11 00 01 10 11 00 01 11 00 01 10 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I Snooze mode standby current ZZ >
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CY7C1352G DC Input Voltage ...................................... −0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage.......................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ..................................... −65°C to +150°C Latch-up Current.............................................
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CY7C1352G [9, 10] Electrical Characteristics Over the Operating Range (continued) Parameter Description Test Conditions Min. Max. Unit I Automatic CE V = Max, Device Deselected, All speeds 45 mA SB4 DD Power-down V ≥ V or V ≤ V , f = 0 IN IH IN IL Current—TTL Inputs [11] Capacitance 100 TQFP Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 3.3V, DD C Clock Input Capacitance 5 pF CLK V = 3.3V DDQ C Input/Output Capacitance 5 pF I/O [11] Therm
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CY7C1352G [16, 17] Switching Characteristics Over the Operating Range –250 –200 –166 –133 Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit [12] t V (typical) to the first Access 11 1 1 ms POWER DD Clock t Clock Cycle Time 4.0 5.0 6.0 7.5 ns CYC t Clock HIGH 1.7 2.0 2.5 3.0 ns CH t Clock LOW 1.7 2.0 2.5 3.0 ns CL Output Times t Data Output Valid After CLK Rise 2.6 2.8 3.5 4.0 ns CO t Data Output Hold After CLK Rise 1.0 1.0 1.5 1.5 ns DOH [13, 14, 15] t Clock to Low-Z 00 0 0 ns
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CY7C1352G Switching Waveforms [18, 19, 20] Read/Write Timing 123 456789 10 t CYC CLK t t t t CENS CENH CL CH CEN t t CES CEH CE ADV/LD WE BW[A:B] A1 A2 A4 ADDRESS A3 A5 A6 A7 t CO t t t DS DH t t t DOH CLZ OEV CHZ t t AS AH Data D(A1) D(A2) Q(A3) Q(A4) Q(A4+1) D(A5) Q(A6) D(A2+1) In-Out (DQ) t OEHZ t DOH t OELZ OE WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D(A1) D(A2) WRITE Q(A3) Q(A4) READ D(A5) Q(A6) D(A7) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED Notes: For this waveform ZZ is t
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CY7C1352G Switching Waveforms (continued) [18, 19, 21] NOP, STALL, and DESELECT Cycles 123 456 789 10 CLK CEN CE ADV/LD WE BW[A:B] A1 A2 A3 A4 A5 ADDRESS t CHZ D(A4) D(A1) Q(A2) Q(A3) Q(A5) Data In-Out (DQ) WRITE READ STALL READ WRITE STALL NOP READ DESELECT CONTINUE D(A1) Q(A2) Q(A3) D(A4) Q(A5) DESELECT DON’T CARE UNDEFINED [22, 23] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Notes: 21. The IGNORE CLOCK EDGE or STALL cycle (Cl
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CY7C1352G Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 133 CY7C1352G-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1352G-133AXI Industrial 166 CY7C1352G-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1
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CY7C1352G Document History Page Document Title: CY7C1352G 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05514 Issue Orig. of REV. ECN NO. Date Change Description of Change ** 224362 See ECN RKF New data sheet *A 288431 See ECN VBL Deleted 100 MHz and 225 MHz Changed TQFP package in Ordering Information section to lead-free TQFP *B 332895 See ECN SYT Modified Address Expansion balls in the pinouts for 100 TQFP Package as per JEDEC standards and updated the Pin De
