Resumen del contenido incluido en la página 1
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
Excellent-Price/Performance Floating-Point 32-Bit External Memory Interface (EMIF)
Digital Signal Processor (DSP): − Glueless Interface to Asynchronous
TMS320C6711D Memories: SRAM and EPROM
− Eight 32-Bit Instructions/Cycle − Glueless Interface to Synchronous
− 167-, 200-, 250-MHz Clock Rates Memories: SDRAM and SBSRAM
− 6-, 5-, 4-ns Instruction Cycle Time − 256M-Byte Total Addressable
Resumen del contenido incluido en la página 2
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 Table of Contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 EMIF big endian mode correctness . . . . . . . . . . . . . . . . 60 GDP and ZDP BGA packages (bottom view) . . . . . . . . . . . . 4 bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 description . . . . . . . . . . . . . . . . . . . . . . . . . .
Resumen del contenido incluido en la página 3
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 REVISION HISTORY The TMS320C6711D device-specific documentation has been split from TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D Floating−Point Digital Signal Processors, literature number SPRS088N, into a separate Data Sheet, literature number SPRS292. It also highlights technical changes made to SPRS292 to gen- erate SPRS292A; these changes are marked by “[Revision A]” in the Revision
Resumen del contenido incluido en la página 4
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 GDP and ZDP BGA packages (bottom view) † GDP and ZDP 272-PIN BALL GRID ARRAY (BGA) PACKAGES (BOTTOM VIEW) Y W V U T R P N M L K J H G F E D C B A 1 3 57 9 11 13 15 17 19 2468 10 12 14 16 18 20 † The ZDP mechanical package designator represents the version of the GDP package with lead−free balls. For more detailed information, see the Mechanical Data section of this document. 4 POST OFFICE BOX 14
Resumen del contenido incluido en la página 5
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 description The TMS320C67x DSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D † devices ) compose the floating-point DSP family in the TMS320C6000 DSP platform. The C6711, C6711B, C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice
Resumen del contenido incluido en la página 6
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 device characteristics Table 1 provides an overview of the C6711D DSP. The table shows significant features of the device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C6000 DSP device part numbers and part numbering, see Figure 5. Table 1. Characteristics of the C6711D Processor INTERNAL CLOCK C6711D HA
Resumen del contenido incluido en la página 7
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 device compatibility The TMS320C6211/C6211B and C6711/C6711B devices are pin-compatible and have the same peripheral set; thus, making new system designs easier and providing faster time to market. The following list summarizes the device characteristic differences among the C6211, C6211B, C6711, C6711B, C6711C, and C6711D devices: The C6211 and C6211B devices have a fixed-point C62x CPU, whil
Resumen del contenido incluido en la página 8
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 functional block and CPU (DSP core) diagram Digital Signal Processor SDRAM ÁÁÁ External SBSRAM 32 Memory L1P Cache ÁÁÁ Interface Direct Mapped SRAM (EMIF) ÁÁÁ 4K Bytes Total ROM/FLASH ÁÁÁ Timer 0 I/O Devices ÁÁÁ ÁÁÁ Timer 1 C6000 CPU (DSP Core) ÁÁÁ Instruction Fetch Control Registers ÁÁÁ Multichannel L2 Instruction Dispatch Buffered Memory Control ÁÁÁ Framing Chips: Serial Port 1 Instruction De
Resumen del contenido incluido en la página 9
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU (DSP core) description The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines
Resumen del contenido incluido en la página 10
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU (DSP core) description (continued) src1 ÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁ ÁÁ † src2 .L1 ÁÁÁÁÁ Á ÁÁÁÁ dst ÁÁÁÁÁ ÁÁ Á 8 long dst 8 ÁÁÁÁÁ Á long src 32 LD1 32 MSB ÁÁÁÁÁ Á Á ST1 32 Register ÁÁÁÁÁ Á long src File A 8 long dst ÁÁÁÁÁ Á (A0−A15) 8 Data Path A dst † ÁÁÁÁÁ .S1 Á src1 ÁÁÁÁÁ Á ÁÁ src2 ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ dst ÁÁÁÁÁ Á Á † src1 .M1 ÁÁÁÁÁ ÁÁ ÁÁ src2 ÁÁÁÁÁ Á ÁÁ Á LD1 32 LSB ÁÁÁÁÁ dst ÁÁ src1 .D1 ÁÁ ÁÁÁÁÁ Á DA1
Resumen del contenido incluido en la página 11
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 memory map summary Table 2 shows the memory map address ranges of the device. Internal memory is always located at address 0 and can be used as both program and data memory. The configuration registers for the common peripherals are located at the same hex address ranges. The external memory address ranges in the device begin at the address location 0x8000 0000. Table 2. TMS320C6711D Memory Map
Resumen del contenido incluido en la página 12
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions Table 3 through Table 14 identify the peripheral registers for the device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names, and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide (literature numb
Resumen del contenido incluido en la página 13
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 5. Interrupt Selector Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Selects which interrupts drive CPU interrupts 10−15 019C 0000 MUXH Interrupt multiplexer high (INT10−INT15) Selects which interrupts drive CPU interrupts 4−9 019C 0004 MUXL Interrupt multiplexer low (INT04−INT09) Sets the polarity of the external interrupts 019C 0008
Resumen del contenido incluido en la página 14
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 2. 31 0 EDMA Parameter Word 0 EDMA Channel Options Parameter (OPT) OPT Word 1 EDMA Channel Source Address (SRC) SRC Word 2 Array/Frame Count (FRMCNT) Element Count (ELECNT) CNT Word 3 EDMA Channel Destination Address (DST) DST Word 4 Array/Frame Index (FRMIDX) Eleme
Resumen del contenido incluido en la página 15
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 10. PLL Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B7 C000 PLLPID Peripheral identification register (PID) [0x00010801 for PLL Controller] 01B7 C004 − 01B7 C0FF − Reserved 01B7 C100 PLLCSR PLL control/status register 01B7 C104 − 01B7 C10F − Reserved 01B7 C110 PLLM PLL multiplier control register 01B7 C114 PLLDIV0 PLL controlle
Resumen del contenido incluido en la página 16
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 13. Timer 0 and Timer 1 Registers HEX ADDRESS RANGE ACRONYM ACRONYM REGISTER NAME REGISTER NAME COMMENTS COMMENTS TIMER 0 TIMER 1 Determines the operating mode of the timer, monitors the 0194 0000 0198 0000 CTLx Timer x control register timer status, and controls the function of the TOUT pin. Contains the number of timer input clock cycles to cou
Resumen del contenido incluido en la página 17
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 signal groups description CLKIN RESET CLKOUT3 NMI ‡ EXT_INT7 Reset and Clock/PLL † CLKOUT2 ‡ Interrupts EXT_INT6 ‡ EXT_INT5 ‡ CLKMODE0 EXT_INT4 PLLHV TMS RSV TDO RSV TDI RSV TCK IEEE Standard • TRST 1149.1 Reserved EMU0 • (JTAG) EMU1 • Emulation EMU2 RSV EMU3 RSV EMU4 RSV EMU5 Control/Status HPI 16 HD[15:0] (Host-Port Interface) Data HAS HCNTL0 HR/W Register Select HCNTL1 HCS Control HDS1 HDS2 H
Resumen del contenido incluido en la página 18
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 signal groups description (continued) 32 ED[31:0] Data ECLKIN ECLKOUT Memory ARE/SDCAS/SSADS CE3 Control CE2 AOE/SDRAS/SSOE Memory Map CE1 AWE/SDWE/SSWE Space Select CE0 ARDY 20 EA[21:2] Address HOLD Bus HOLDA Arbitration BE3 BUSREQ BE2 Byte Enables BE1 BE0 EMIF (External Memory Interface) TOUT1 TOUT0 Timer 1 Timer 0 TINP0 TINP1 Timers McBSP1 McBSP0 CLKX1 CLKX0 FSX1 Transmit Transmit FSX0 DX1 DX0
Resumen del contenido incluido en la página 19
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 signal groups description (continued) GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5) GP[4](EXT_INT4) GPIO CLKOUT2/GP[2] General-Purpose Input/Output (GPIO) Port Figure 4. Peripheral Signals (Continued) 19 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Resumen del contenido incluido en la página 20
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS On this device, bootmode and certain device configurations/peripheral selections are determined at device reset. Also, other device configurations (e.g., EMIF input clock source) are software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200] after device reset. device configurations at device reset Table 15 describes the C6711D devi
