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TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007
1 TMS320DM355 Digital Media System-on-Chip (DMSoC)
1.1 Features
encoder
• High-Performance Digital Media
System-on-Chip • External Memory Interfaces (EMIFs)
– 216- and 270-MHz ARM926EJ-S Clock Rate – DDR2 and mDDR SDRAM 16-bit wide EMIF
With 256 MByte Address Space (1.8-V I/O)
– Fully Software-Compatible With ARM9
– Asynchronous16-/8-bit Wide EMIF (AEMIF)
• ARM926EJ-S Core
• Flash Memory In
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PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 – IEEE-1149.1 (JTAG) • 337-Pin Ball Grid Array (BGA) Package Boundary-Scan-Compatible (ZCE Suffix), 0.65-mm Ball Pitch – ETB (Embedded Trace Buffer) with • 90nm Process Technology 4K-Bytes Trace Buffer memory • 3.3-V and 1.8-V I/O, 1.3-V Internal – Device Revision ID Readable by ARM 2 TMS320DM355 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback
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TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 1.2 Description The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low cost portable digital video applications. Designed to offer portable video designers and manufacturers the ability to produce affordable portable digital video solutions with
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er c PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the DM355 device. CCD/ CCDC CCD IPIP IPIPE CMOS C E Module LD/CM 3A LD / Enhanced 3A DDR VPFE Enhanced DMA DL DDR DLL/ 16 bit DDR2/MDDR 16 64 channels channels controller PHY 3PCC /TC MH 10b Composite video Vide Video DAC (100 MHz OSD OS z ) Encod Encoder o Digital RGB/YUV D er VPBE VPSS DMA /
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TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 Contents 1 TMS320DM355 Digital Media System-on-Chip 4.2 Recommended Operating Conditions............... 92 (DMSoC) ................................................... 1 4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case 1.1 Features .............................................. 1 Temperature (Unless Otherwise Noted) ............ 93 1.2 Description..
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PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the DMSoC. The table shows significant features of the device, including the peripherals, capacity of on-chip RAM, ARM operating frequency, the package type with pin count, etc. Table 2-1. Characteristics of the Processor HARDWARE FEATURES DM355 DDR2 / mDDR Memory Controller DDR2 / mDDR (16-bit bu
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TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 2.2 Memory Map Summary Table 2-3 shows the memory map address ranges of the device. Table 2-3 depicts the expanded map of the Configuration Space (0x01C0 0000 through 0x01FF FFFF). The device has multiple on-chip memories associated with its processor and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of de
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PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 Table 2-3. DM355 ARM Configuration Bus Access to Peripherals (continued) Address Accessibility UART1 0x01C2 0400 0x01C2 07FF 1K √ √ Timer4/5 0x01C2 0800 0x01C2 0BFF 1K √ √ Real-time out 0x01C2 0C00 0x01C2 0FFF 1K √ √ I2C 0x01C2 1000 0x01C2 13FF 1K √ √ Timer0/1 0x01C2 1400 0x01C2 17FF 1K √ √ Timer2/3 0x01C2 1800 0x01C2 1BFF 1K √ √ WatchDog Timer 0x01C2 1C00 0x01C2 1FFF 1K √ √
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TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 2.3 Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. 2.3.1 Pin Map (Bottom View) Figure 2-1 through Figure 2-4 show the pin assignments in four quadrants
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PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 1 2 3 4 5 6 7 8 9 V DDR_A02 DDR_A03 DDR_A05 DDR_A08 DDR_A09 DDR_A11 DDR_CLK DDR_CLK W SS V DDR_BA[2] DDR_CAS V DDR_A00 DDR_A01 DDR_A04 DDR_A07 DDR_A10 DDR_A12 SS V V V V DDR_BA[1] DDR_BA[0] V U DDR_A06 DDR_A13 SS SS SS SS SS V V T MXO2 PCLK DDR_RAS DDR_CS DDR_ZN SS SS V V CV CV V R MXI2 YIN3 CAM_VD CAM_WEN_ SS SS DD DD DD_DDR FIELD V V V V P V YIN1 YIN4 YIN2 YIN0 DD_VIN DD_V
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TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 10 11 12 13 14 15 16 17 18 19 DDR_WE DDR_DQ01 DDR_DQ05 DDR_DQ07 DDR_DQ10 DDR_DQ11 DDR_DQ13 DDR_DQ15 DDR_GATE0 CV W DD DDR_DQ00 DDR_DQS[0] DDR_DQS[1] DDR_DQ14 DDR_GATE1 V DDR_CKE DDR_DQ06 DDR_DQ09 EM_A13 V SS DDR_VREF V DDR_DQM[1] DDR_DQ12 V UART0_RXD DDR_DQ02 DDR_DQ04 DDR_DQ08 EM_A12 U SS SS V DDR_DQM[0] V CV UART0_TXD DDR_DQ03 DD_DDR SS EM_A08 T DD V V V UART1_RXD UART1_TXD DDA33_DDRDLL SS
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PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 V CV CV CV V EM_WE EM_CE0 EM_D01 EM_D03 EM_D05 DD DD DD SS J SS V CV V CV V ASP0_DX EM_ADV CV EM_D00 EM_D02 SS SSA_PLL1 DD SS DD H DD V CV V GIO003 ASP0_FSX EM_WAIT EM_CE1 DD DDA_PLL1 G DD V V V V V GIO002 ASP0_FSR ASP0_CLKR ASP0_CLKX EM_OE DD DD DD DD DD F SPI1_ V ASP1_FSX ASP1_FSR ASP0_DR TCK RTCK SPI1_SDO GIO001 SS EM_CLK E SDENA[0] MMCSD0_ ASP1_CLKS ASP1_CLKR ASP1_CLKX R
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TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 2.4 Pin Functions The pin functions tables (Table 2-4 through Table 2-22) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/sha
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PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 Table 2-5. CCD Controller/Video Input Terminal Functions TERMINAL (1) (2)(3) TYPE OTHER DESCRIPTION NAME NO. Standard CCD Analog Front End (AFE): NOT USED • YCC 16-bit: Time multiplexed between chroma: CB/SR[07] CIN7/ PD • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO101/ N3 I/O/Z V DD_VIN multiplexed between luma and chroma of the upper channe
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TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 Table 2-5. CCD Controller/Video Input Terminal Functions (continued) TERMINAL (1) (2)(3) TYPE OTHER DESCRIPTION NAME NO. Standard CCD Analog Front End (AFE): Raw[05] • YCC 16-bit: Time multiplexed between chroma: Y[05] YIN5/ PD M5 I/O/Z • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO091 V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR
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PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 Table 2-6. Signals for VPBE Display Modes PIN NAME YCC16 YCC8/ PRGB SRGB REC656 HSYNC HSYNC HSYNC HSYNC HSYNC GIO073 VSYNC VSYNC VSYNC VSYNC VSYNC GIO072 LCD_OE As needed As needed As needed As needed GIO071 FIELD As needed As needed As needed As needed GIO070 R2 PWM3C EXTCLK As needed As needed As needed As needed GIO069 B2 PWM3D VCLK VCLK VCLK VCLK VCLK GIO068 YOUT7 Y7 Y7,
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TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 Table 2-7. Digital Video Terminal Functions TERMINAL (1) (2)(3) (4) TYPE OTHER DESCRIPTION NAME NO. YOUT7-R7 C3 I/O/Z V Digital Video Out: VENC settings determine function DD_VOUT YOUT6-R6 A4 I/O/Z V Digital Video Out: VENC settings determine function DD_VOUT YOUT5-R5 B4 I/O/Z V Digital Video Out: VENC settings determine function DD_VOUT YOUT4-R4 B3 I/O/Z V Digital Video Out: VENC settings
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PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 Table 2-8. Analog Video Terminal Functions TERMINAL (1) (2) TYPE OTHER DESCRIPTION NAME NO. Video DAC: Reference voltage output (0.45V, 0.1uF to GND). When the DAC is not VREF J7 A I/O/Z used, the VREF signal should be connected to V . SS Video DAC: Pre video buffer DAC output (1000 ohm to VFB). When the DAC is not IOUT E1 A I/O/Z used, the IOUT signal should be connected to
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TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued) TERMINAL (1) (2)(3) TYPE OTHER DESCRIPTION NAME NO. EM_A06/ Async EMIF: Address bus bit[06] P18 I/O/Z V DD GIO060 GIO: GIO[60] EM_A05/ Async EMIF: Address bus bit[05] R19 I/O/Z V DD GIO059 GIO: GIO[59] EM_A04/ Async EMIF: Address bus bit[04] P15 I/O/Z V DD GIO058 GIO: GIO[58] EM_A03/ Async EMIF: Address bus bit[03] N18
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PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A–SEPTEMBER 2007–REVISED SEPTEMBER 2007 Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued) TERMINAL (1) (2)(3) TYPE OTHER DESCRIPTION NAME NO. Async EMIF: Lowest numbered chip select. Can be programmed to be used for EM_CE0/ standard asynchronous memories (example: flash), OneNAND, or NAND J16 I/O/Z V DD GIO037 memory. Used for the default boot and ROM boot modes. GIO: GIO[037] Async EMIF: Se
