Résumé du contenu de la page N° 1
STK22C48
16 Kbit (2K x 8) AutoStore nvSRAM
Features Functional Description
■ 25 ns and 45 ns access times The Cypress STK22C48 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
■ Hands off automatic STORE on power down with external 68
elements incorporate QuantumTrap technology producing the
µF capacitor
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
■ STORE to QuantumTrap™ n
Résumé du contenu de la page N° 2
STK22C48 Pin Configurations Figure 1. Pin Diagram - 28-Pin SOIC V 1 28 V CAP CC NC 2 27 WE A 3 7 26 HSB A 6 4 25 A 8 A 5 24 A 5 9 A 4 6 NC 23 28-SOIC A 3 7 22 OE Top View A 2 8 21 A 10 (Not To Scale) A 9 20 1 CE A 0 10 19 DQ7 11 18 DQ0 DQ6 DQ1 12 17 DQ5 13 16 DQ2 DQ4 V 14 SS 15 DQ3 Table 1. Pin Definitions Pin Name Alt IO Type Description A –A Input Address Inputs. Used to select one of the 2,048 bytes of the nvSRAM. 0 10 DQ -DQ Input or Output Bidirectional Data IO Lines. Used as input or out
Résumé du contenu de la page N° 3
STK22C48 Figure 2. AutoStore Mode Device Operation The STK22C48 nvSRAM is made up of two functional compo- nents paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells
Résumé du contenu de la page N° 4
STK22C48 Figure 3. AutoStore Inhibit Mode Data Protection The STK22C48 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and Write operations. The low voltage condition is detected when V is CC less than V . If the STK22C48 is in a Write mode (both CE SWITCH and WE are low) at power up after a RECALL or after a STORE, the Write is inhibited until a negative transition on CE or WE is detected. This protects ag
Résumé du contenu de la page N° 5
STK22C48 Figure 4. Current Versus Cycle Time (Read) device drives HSB LOW for 20 ns at the onset of a STORE. When the STK22C48 is connected for AutoStore operation (system V connected to V and a 68 μF capacitor on V ) CC CC CAP and V crosses V on the way down, the STK22C48 CC SWITCH attempts to pull HSB LOW. If HSB does not actually get below V , the part stops trying to pull HSB LOW and abort the STORE IL attempt. Best Practices nvSRAM products have been used effectively for over 15 years. Whi
Résumé du contenu de la page N° 6
STK22C48 Voltage on DQ or HSB .......................–0.5V to Vcc + 0.5V Maximum Ratings 0-7 Power Dissipation ......................................................... 1.0W Exceeding maximum ratings may shorten the useful life of the DC Output Current (1 output at a time, 1s duration).... 15 mA device. These user guidelines are not tested. Storage Temperature ................................. –65 °C to +150 °C Operating Range Temperature under bias.............................. –55 °C to +125 °
Résumé du contenu de la page N° 7
STK22C48 Capacitance [5] In the following table, the capacitance parameters are listed. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, 8pF IN A V = 0 to 3.0V CC C Output Capacitance 7pF OUT Thermal Resistance [5] In the following table, the thermal resistance parameters are listed. 28-SOIC 28-SOIC Parameter Description Test Conditions Unit (300 mil) (330 mil) Θ Thermal Resistance Test conditions follow standard test methods TBD TBD °C/W JA (Junction to
Résumé du contenu de la page N° 8
STK22C48 AC Switching Characteristics SRAM Read Cycle Parameter 25 ns 45 ns Description Unit Cypress Alt Min Max Min Max Parameter t t Chip Enable Access Time 25 45 ns ACE ELQV [6] t t t Read Cycle Time 25 45 ns RC AVAV, ELEH [7] t t Address Access Time 25 45 ns AA AVQV t t Output Enable to Data Valid 10 20 ns DOE GLQV [7] t t Output Hold After Address Change 5 5 ns OHA AXQX [8] t t Chip Enable to Output Active 5 5 ns LZCE ELQX [8] t t Chip Disable to Output Inactive 10 15 ns HZCE EHQZ [8] t t
Résumé du contenu de la page N° 9
STK22C48 SRAM Write Cycle Parameter 25 ns 45 ns Description Unit Cypress Alt Min Max Min Max Parameter t t Write Cycle Time 25 45 ns WC AVAV t t t Write Pulse Width 20 30 ns PWE WLWH, WLEH t t t Chip Enable To End of Write 20 30 ns SCE ELWH, ELEH t t t Data Setup to End of Write 10 15 ns SD DVWH, DVEH t t t Data Hold After End of Write 0 0 ns HD WHDX, EHDX t t t Address Setup to End of Write 20 30 ns AW AVWH, AVEH t t t Address Setup to Start of Write 0 0 ns SA AVWL, AVEL t t t Address Hold Aft
Résumé du contenu de la page N° 10
STK22C48 AutoStore or Power Up RECALL STK22C48 Parameter Alt Description Unit Min Max [12] t t Power up RECALL Duration 550 μs HRECALL RESTORE [14, 15] t t STORE Cycle Duration 10 ms STORE HLHZ [13] t t t Time Allowed to Complete SRAM Cycle 1 μs DELAY HLQZ , BLQZ V Low Voltage Trigger Level 4.0 4.5 V SWITCH V Low Voltage Reset Level 3.6 V RESET [10] t Low Voltage Trigger (V ) to HSB Low 300 ns VSBL SWITCH Switching Waveform Figure 11. AutoStore/Power Up RECALL WE Notes 12. t starts from the t
Résumé du contenu de la page N° 11
STK22C48 Hardware STORE Cycle STK22C48 Parameter Alt Description Unit Min Max [13, 16] t t t Hardware STORE High to Inhibit Off 700 ns DHSB RECOVER, HHQX t t Hardware STORE Pulse Width 15 ns PHSB HLHX t Hardware STORE Low to STORE Busy 300 ns HLBL Switching Waveform Figure 12. Hardware STORE Cycle Note 16. t is only applicable after t is complete. DHSB STORE Document Number: 001-51000 Rev. ** Page 11 of 14 [+] Feedback
Résumé du contenu de la page N° 12
STK22C48 STK22C48 - N F 45 I TR Packaging Option: TR = Tape and Reel Blank = Tube Temperature Range: Blank - Commercial (0 to 70°C) I - Industrial (-40 to 85°C) Speed: 25 - 25 ns 45 - 45 ns Lead Finish F = 100% Sn (Matte Tin) Package: N = Plastic 28-pin 300 mil SOIC S = Plastic 28-pin 330 mil SOIC Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 25 STK22C48-NF25TR 51-85026 28-pin SOIC (300 mil) Commercial STK22C48-NF25 51-85026 28-pin SOIC (300 mil) S
Résumé du contenu de la page N° 13
STK22C48 Package Diagrams Figure 13. 28-Pin (300 mil) SOIC (51-85026) NOTE : PIN 1 ID 1. JEDEC STD REF MO-119 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. 14 1 MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX. 0.291[7.39] 4. PACKAGE WEIGHT 0.85gms 0.300[7.62] * 0.394[10.01] 0.419[10.64] PART # 15 28 0.026[0.66] S28.3 STANDARD PKG. 0.032[0.81] S
Résumé du contenu de la page N° 14
STK22C48 Document History Page Document Title: STK22C48 16 Kbit (2K x 8) AutoStore nvSRAM Document Number: 001-51000 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 2625139 GVCH/PYRS 01/30/09 New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products P
