Résumé du contenu de la page N° 1
CMOS 8-BIT SINGLE CHIP MICROCOMPUTER
S1C88650
Technical Manual
S1C88650 Technical Hardware
Résumé du contenu de la page N° 2
NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level re
Résumé du contenu de la page N° 3
Configuration of product number Devices S1 C 88104 F 0A01 00 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G : TCP BT 4 directions 0H : TCP BD 4 directions 0J : TCP SL 2 directions 0K : TCP SR 2 directions 0L : Tape & reel LEFT 0M : TCP ST 2 directions 0N : TCP SD 2 directions 0P : TCP ST 4 di
Résumé du contenu de la page N° 4
Résumé du contenu de la page N° 5
CONTENTS Contents 1 INTRODUCTION .............................................................................................. 1 1.1 Features .............................................................................................................................1 1.2 Block Diagram ...................................................................................................................2 1.3 Pins ......................................................................................
Résumé du contenu de la page N° 6
CONTENTS 5.3 Watchdog Timer ................................................................................................................39 5.3.1 Configuration of watchdog timer ............................................................................................ 39 5.3.2 Interrupt function .................................................................................................................... 39 5.3.3 Control of watchdog timer ..............................................
Résumé du contenu de la page N° 7
CONTENTS 5.10.8 Setting frame frequency for LCD driver ............................................................................... 94 5.10.9 Control of programmable timer ............................................................................................95 5.10.10 Programming notes ............................................................................................................ 107 5.11 LCD Driver ...........................................................................
Résumé du contenu de la page N° 8
CONTENTS APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL (Peripheral Circuit Board for S1C88650) ...................................... 163 A.1 Names and Functions of Each Part .................................................................................163 A.2 Precautions ......................................................................................................................165 A.2.1 Precaution for operation .................................................................
Résumé du contenu de la page N° 9
1 INTRODUCTION 1 INTRODUCTION The S1C88650 is an 8-bit microcomputer for other characters and user-defined characters, this portable equipment with an LCD display that has a makes it possible to display kanji characters built-in LCD controller/driver and a character without any external kanji font ROM (refer to generator (kanji) ROM. This microcomputer Appendix B, "USING KANJI FONT"). This 8-bit features low-voltage (1.8 V) and high-speed (8.2 CPU has up to 16MB accessible address space MHz) op
Résumé du contenu de la page N° 10
1 INTRODUCTION 1.2 Block Diagram Core CPU S1C88 OSC1, 2 Oscillator Interrupt Controller OSC3, 4 MCU/MPU K00–K02 K03 (BREQ) BREQ (K03) System Controller Input Port BACK (R33) K04–K07 P10 (SIN) RESET Reset/Test I/O Port P11 (SOUT) TEST P12 (SCLK) P13 (SRDY) P14 (TOUT0/TOUT1) Watchdog Timer Serial Interface P15 (TOUT2/TOUT3) P16 (FOUT) EXCL0–EXCL3 (K04–K07) P17 (TOUT2/TOUT3) External Programmable Timer TOUT0–TOUT3 (P14, P15) P00–P07 (D0–D7) Memory Interface /Event Counter TOUT2/TOUT3 (P17) R00–R07
Résumé du contenu de la page N° 11
1 INTRODUCTION 1.3 Pins 1.3.1 Pin layout diagram QFP22-256pin 192 129 193 128 INDEX 256 65 1 64 Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 N.C. 53 SEG88 105 COM23 157 P07/D7 209 COM11 2 N.C. 54 SEG89 106 COM22 158 P06/D6 210 COM12 3 TEST 55 SEG90 107 COM21 159 P05/D5 211 COM13 4 SEG39 56 SEG91 108 COM20 160 P04/D4 212 COM14 5 SEG40 57 SEG92 109 COM19 161 P03/D3 213 COM15 6 SEG41 58 SEG93 110 COM18 162 P02/D2 214 SEG0 7 SEG42 59 SEG94 111 COM17 163 P01
Résumé du contenu de la page N° 12
1 INTRODUCTION 1.3.2 Pin description Table 1.3.2.1 S1C88650 pin description Pin name Pin No. In/Out Function VDD 131, 189 – Power supply (+) terminal VSS 67, 134, 195, 253 – Power supply (GND) terminal VD1 135 – Internal logic system and oscillation system voltage regulator output terminals VD2 113 – LCD circuit power voltage booster output terminal VC1–VC5 125–121 – LCD drive voltage output terminals CA–CG 120–114 – LCD and power voltage booster capacitor connection terminals OSC1 136 I OSC1
Résumé du contenu de la page N° 13
1 INTRODUCTION Select the specifications that meet the target system 1.4 Mask Option and check the appropriate box. Mask options shown below are provided for the The option selection is done interactively on the S1C88650. screen during function option generator winfog Several hardware specifications are prepared in execution, using this option list as reference. Mask each mask option, and one of them can be selected pattern of the IC is finally generated based on the according to the applicatio
Résumé du contenu de la page N° 14
1 INTRODUCTION 5 I/O PORT PULL UP RESISTOR • P00 ......... ■■ 1. With Resistor ■■ 2. Gate Direct This mask option can select whether the pull-up resistor for the I/O port terminal (it works during input mode) is • P01 ......... ■■ 1. With Resistor ■■ 2. Gate Direct used or not. It is possible to select for each bit of the I/O • P02 ......... ■■ 1. With Resistor ■■ 2. Gate Direct ports. Refer to Section 5.7, "I/O Ports (P ports)", for • P03 ......... ■■ 1. With Resistor ■■ 2. Gate Direct detail
Résumé du contenu de la page N° 15
2 POWER SUPPLY 2POWER SUPPLY In this section, we will explain the operating voltage and the configuration of the internal power supply circuit of the S1C88650. Either or can be selected as the 2.1 Operating Voltage power source for the LCD system voltage regulator The S1C88650 operating power voltage is as according to the power supply voltage follows: level. 1.8 V to 3.6 V Table 2.2.2 Power source for LCD system voltage regulator 2.2 Internal Power Supply Circuit Supply volt
Résumé du contenu de la page N° 16
3 CPU AND BUS CONFIGURATION 3 CPU AND BUS CONFIGURATION In this section, we will explain the CPU, operating mode and bus configuration. 3.2.2 RAM 3.1 CPU The internal RAM capacity is 8K bytes and is The S1C88650 utilize the S1C88 8-bit core CPU allocated to 00D800H–00F7FFH. whose resistor configuration, command set, etc. are Even when external memory which overlaps the virtually identical to other units in the family of internal RAM area is expanded, the RAM area is processors incorporating the
Résumé du contenu de la page N° 17
3 CPU AND BUS CONFIGURATION When multiple exception processing factors are 3.3 Exception Processing Vectors generated at the same time, execution starts with 000000H–00004BH in the program area of the the highest priority item. S1C88650 is assigned as exception processing The priority sequence shown in Table 3.3.1 assumes vectors. Furthermore, from 00004EH to 0000FFH, that the interrupt priority levels are all the same. software interrupt vectors are assignable to any two The interrupt priority
Résumé du contenu de la page N° 18
3 CPU AND BUS CONFIGURATION When accessing internal memory in this mode, ____ ____ _____ 3.5.2 Bus mode the chip enable (CE) and read (RD)/write (WR) In order to set bus specifications to match the signals are not output to external memory, and configuration of external expanded memory, two the data bus (D0–D7) goes into high impedance different bus modes described below are selectable status (or pull-up status). in software. Consequently, in cases where addresses overlap in external and intern
Résumé du contenu de la page N° 19
3 CPU AND BUS CONFIGURATION - MCU mode - - MPU mode - 3.6 External Bus 3FFFFFH The S1C88650 has bus terminals that can address a 2FFFFFH maximum of 1M × 3 bytes and memory (and other) devices can be externally expanded according to External : the range of each bus mode described in the memory area previous section. External memory area Address bus (A0–A19) 100000H Data bus (D0–D7) Unused area S1C88650 0F0000H 0EFFFFH BREQ External External External BACK device device device 010000H Internal m
Résumé du contenu de la page N° 20
3 CPU AND BUS CONFIGURATION ____ _____ When set as read (RD)/write (WR) signal output 3.6.2 Address bus terminal, the data register and high impedance The S1C88650 possesses a 20-bit external address control register for each output port (R24, R25) are bus A0–A19. The terminals and output circuits of detached from the output circuit and is usable as a address bus A0–A19 are shared with output ports general purpose data register with read/write R00–R07 (=A0–A7), R10–R17 (=A8–A15) and R20– capabi
