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USBS6
V 0.3 June 29, 2010 User Manual C1030-5510
TM
SPARTAN-6 FPGA board with USB2.0,
SPI-Flash and JTAG interface.
Order number: C1030-5510
USBS6 / C1030-5510 http://www.cesys.com/
User Doc V0.3 -1- preliminary
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Copyright information Copyright © 2010 CESYS GmbH. All Rights Reserved. The information in this document is proprietary to CESYS GmbH. No part of this document may be reproduced in any form or by any means or used to make derivative work (such as translation, transformation or adaptation) without written permission from CESYS GmbH. CESYS GmbH provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and impl
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Overview Summary of USBS6 TM USBS6 is a low-cost multilayer PCB with SPARTAN-6 FPGA and USB 2.0 Interface. 34 I/O balls of the FPGA are available on standard 2.54mm headers, 81 I/O balls can be reached through a industry standard VG 96-pin connector. It offers multiple configuration options including USB and onboard SPI-Flash and can also be used standalone without the need of a USB interface. Feature list Form factor 120x100mm TM XILINX SPARTAN-6 XC6SLX16-2CSG324C TM USB2.0 Controller CYPR
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Hardware Block Diagram 1 Gb low-power 128Mb DDR SDRAM QSPI Flash 64kb I²C EEPROM XILINX FPGA USB2.0 Spartan-6 CYPRESS FX-2 Oscillator Oscillator 48 MHz 24 MHz 16Mb SPI Flash Peripherals JTAG for configuration USB / OSC OSC SERIAL Optional 3 status & USB to HEX rotary Oscillators 5 user LEDs UART DIP switch Figure 1: USBS6 Block Diagram TM Spartan-6 FPGA XC6SLX16-2CSG324C FPGA features: Logic cells 14,579 Configurable logic blocks (Slices / Flip-Flops) 2,278 / 18,224 Max distributed RAM (kb) 136
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Figure 2: USBS6 Top View USBS6 / C1030-5510 http://www.cesys.com/ User Doc V0.3 -5- preliminary
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Powering USBS6 USBS6 may be used bus-powered (see SW2 below) without the need of any external power supply other than USB. In this mode VCCO_IO on J3,PIN A3, B3, C3 sourcing capability is limited due to the fact, that USB power supply current is limited depending on which system is used as host. Typically USB hosts allow up to 500mA. In bus-powered mode, at first only FX2 is enabled. After successful connection to the operating system the further power-on sequencing behavior depends on UDK
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TM ! It is strongly recommended to check XILINX UG381 about Spartan-6 FPGA SelectIO TM Signal Standards on XILINX website. Configuration Configuration of USBS6 can be accomplished in several ways: JTAG, SPI-Flash or USB. The default configuration mode is booting from SPI-Flash. After powering on the FPGA, USBS6 always tries to configure itself from the attached Flash using SPI Master mode. If no valid design is stored in the SPI-Flash the FPGA has to be configured via JTAG or USB. JTAG conf
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TM FPGA the reader is encouraged to take a look at the user guide UG380 on XILINX web page. USB2.0 controller TM TM CYPRESS FX2LP is a highly integrated, low power USB2.0 microcontroller, that integrates USB2.0 transceiver, serial interface engine (SIE), enhanced 8051 micro- TM controller and a programmable peripheral interface. More information on usage of FX2LP in conjunction with Spartan-6 can be found in chapter C. TM TM USB2.0 FX2LP Microcontroller CYPRESS CY7C68013A Signal Name FPGA IO
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TM TM USB2.0 FX2LP Microcontroller CYPRESS CY7C68013A Signal Name FPGA IO Comment FX2_FD11 U13 FX2_FD12 V13 FX2_FD13 U10 FX2_FD14 R8 FX2_FD15 T8 External memory USBS6 offers the opportunity to use various external memory architectures in one´s FPGA design. With Micron Technology MT46H64M16LFCK-5 up to 1Gbit of high-speed low- TM power DDR SDRAM is available. The integrated memory controller of Spartan-6 devices enables system designers to implement state-of-the-art memory interfaces without th
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LPDDR SDRAM MT46H64M16LFCK-5 Signal Name FPGA IO Comment MCB1_RAS_n K15 MCB1_CAS_n K16 Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. * MCB1_WE_n K12 MCB1_CS_n -- MCB1_CKE_n D17 Clock enable: CKE HIGH activates, and CKE LOW deactivates, the internal clock signals, input buffers, and output drivers. Taking CKE LOW enables PRECHARGE power-down and SELF REFRESH operations (all banks idle), or ACTIVE power-down (row active in any bank). CKE is synchronous
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LPDDR SDRAM MT46H64M16LFCK-5 Signal Name FPGA IO Comment MCB1_DQ12 T17 MCB1_DQ13 T18 MCB1_DQ14 U17 MCB1_DQ15 U18 MCB1_UDQS N15 Data strobe for Upper Byte Data bus: Output with read data, input with write data. DQS is edge-aligned with read data, center-aligned in write data. It is used to capture data. * As the memory device interface of Spartan-6 supports only one device, CS# signal is not supported by Spartan-6 MCB. CS# is pulled LOW via an external 0 Ohm resistor. TM TM ! It is stron
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configurable LEDs allow to make internal monitoring status signals visible by driving the appropriate FPGA IO to a HIGH level. Figure 4: Bitte durch Orginalbild ersetzen LEDs Signal Name FPGA IO Comment SYS_LED0 -- Internal 5V power supply. SYS_LED1 -- Power OK- signal from onboard voltage regulator. SYS_LED2 V17 Illuminates to indicate the status of the DONE pin if FPGA is successfully configured. USER_LED0 P7 User- configurable LED. USER_LED1 N7 User- configurable LED. USER_LED2 P8 User- con
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HEX rotary DIP switch DIAL FPGA Pin N8 FPGA Pin M11 FPGA Pin M10 FPGA Pin N9 5 0 1 0 1 6 1 0 0 1 7 0 0 0 1 8 1 1 1 0 9 0 1 1 0 A 1 0 1 0 B 0 0 1 0 C 1 1 0 0 D 0 1 0 0 E 1 0 0 0 F 0 0 0 0 FT232R from FTDI is a USB to serial UART interface. USB to serial UART interface Signal Name FPGA IO Direction Comment FTDI_TXD U15 FPGA IN Transmit asynchronous data output for FT232R. FTDI_RXD V15 FPGA OUT Receiving asynchronous data input for FT232R. FTDI_RTS_n N11 FPGA IN Request to send control output for F
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Figure 5: VG 96-pin external expansion connector J3 J3 VG 96-pin external expansion connector PIN FPGA Comment PIN FPGA Comment PIN FPGA Comment IO IO IO A32 -- GND B32 -- GND C32 -- GND A31 F13 VG96_IO78 B31 E13 VG96_IO79 C31 C4 VG96_IO80 A30 F12 VG96_IO75 B30 E12 VG96_IO76 C30 F11 VG96_IO77 A29 D11 VG96_IO72* B29 C11 VG96_IO73* C29 E11 VG96_IO74 A28 G11 VG96_IO69 B28 F10 VG96_IO70 C28 G8 VG96_IO71 A27 G9 VG96_IO66 B27 F9 VG96_IO67 C27 F8 VG96_IO68 A26 D9 VG96_IO63* B26 C9 VG96_IO64* C26 D8 V
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J3 VG 96-pin external expansion connector PIN FPGA Comment PIN FPGA Comment PIN FPGA Comment IO IO IO A7 N2 VG96_IO9 B7 N1 VG96_IO10 C7 N4 VG96_IO11 A6 P2 VG96_IO6 B6 P1 VG96_IO7 C6 N3 VG96_IO8 A5 T2 VG96_IO3 B5 T1 VG96_IO4 C5 P4 VG96_IO5 A4 U2 VG96_IO0 B4 U1 VG96_IO1 C4 P3 VG96_IO2 A3 -- VCCO_IO B3 -- VCCO_IO C3 -- VCCO_IO A2 -- GND B2 -- GND C2 -- GND A1 -- 5.0V_EXT B1 -- 5.0V_EXT C1 -- 5.0V_EXT * GCLK Figure 6: IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expans
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J4 IDC 2x25-Pin external expansion connector PIN FPGA IO Comment PIN FPGA IO Comment 25 B11 ADD_IO16 26 A11 ADD_IO17 27 B12 ADD_IO18 28 A12 ADD_IO19 29 B14 ADD_IO20 30 A14 ADD_IO21 31 B16 ADD_IO22 32 A16 ADD_IO23 33 -- GND 34 -- GND 35 C10 ADD_IO24* 36 A10 ADD_IO25* 37 D12 ADD_IO26 38 C12 ADD_IO27 39 -- GND 40 -- GND 41 C13 ADD_IO28 42 A13 ADD_IO29 43 D14 ADD_IO30 44 C14 ADD_IO31 45 C15 ADD_IO32 46 A15 ADD_IO33 47 D4 HSWAPEN** 48 -- GND 49 -- VCCO_IO 50 -- GND * GCLK ** Enable / Disable opt
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FPGA design Cypress FX-2 LP and USB basics Several data transfer types are defined in USB 2.0 specification. High-speed bulk transfer is the one and only mode of interest to end users. USB transfers are packet oriented and have a time framing scheme. USB packets consist of USB protocol and user payload data. Payload could have a variable length of up to 512 bytes per packet. Packet size is fixed to the maximum value of 512 bytes for data communication with CESYS USB cards to achieve highest
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In FPGA designs with multiple clock domains asynchronous FIFOs have to be used for transferring data from one clock domain to the other and comprehensive control signals have to be resynchronized. TM Other clock sources can be added internally by using Spartan-6 onchip digital clock managers (DCMs) or PLLs or externally by connecting clock sources to other FPGA global clock inputs. A wide range of clock frequencies can be synthesized with DCMs and PLLs. TM For further details on DCMs/PLLs
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VHDL. Verilog and schematic entry design flows are not supported. • The design “usbs6_soc” demonstrates the implementation of a system-on-chip (SoC) with host software access to the peripherals like GPIOs, external Flash Memory, LPDDR Memory and internal BlockRAM over USB. This design requires a protocol layer over the simple USB bulk transfer (see CESYS application note “Transfer Protocol for CESYS USB products” for details), which is already provided by CESYS software API. • The design “us
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After ProgramFPGA() is called and the FPGA design is completely downloaded, the pin #RESET (note: the prefix # means, that the signal is active low) is automatically pulsed (HIGH/LOW/HIGH). This signal can be used for resetting the FPGA design. The API- function ResetFPGA() can be called to initiate a pulse on #RESET at a user given time. The following sections will give you a brief introduction about the data transfer from and to the FPGA over the Cypress FX-2 USB peripheral controller's sla
