ページ1に含まれる内容の要旨
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
Advanced Multibus Architecture With Three Arithmetic Instructions With Parallel Store
Separate 16-Bit Data Memory Buses and and Parallel Load
One Program Memory Bus
Conditional Store Instructions
40-Bit Arithmetic Logic Unit (ALU),
Fast Return From Interrupt
Including a 40-Bit Barrel Shifter and Two
On-Chip Peripherals
Independent 40-Bit Accumulators
– Software-Programmable Wait-State
ページ2に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 TABLE OF CONTENTS Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Terminal Functions . . . . . . . . .
ページ3に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 description The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’5402 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and addit
ページ4に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 description (continued) †‡ TMS320VC5402 PGE PACKAGE (TOP VIEW) NC 1 108 A18 2 NC 107 A17 V 3 106 V SS SS DV 4 105 A16 DD 5 A10 104 D5 6 HD7 103 D4 7 A11 102 D3 8 A12 101 D2 9 A13 100 D1 10 99 A14 D0 11 98 A15 RS 12 97 NC X2/CLKIN 13 96 HAS X1 14 95 V HD3 SS 15 94 NC CLKOUT 16 93 CV V DD SS 17 92 HCS HPIENA 18 91 HR/W CV DD 19 90 READY NC PS 20 89 TMS DS 21 88 TCK IS 22 87 TRST R/W 23 86 TDI MSTRB 24 8
ページ5に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 description (continued) TMS320VC5402 GGU PACKAGE (BOTTOM VIEW) 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N The pin assignments table to follow lists each signal quadrant and BGA ball number for the TMS320VC5402GGU (144-pin BGA) package which is footprint-compatible with the ’LC548 and ’LC/VC549 devices. 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ページ6に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 † Pin Assignments for the TMS320VC5402GGU (144-Pin BGA) Package SIGNAL SIGNAL SIGNAL SIGNAL BGA BALL # BGA BALL # BGA BALL # BGA BALL # NAME NAME NAME NAME NC A1 NC N13 NC N1 A19 A13 NC B1 NC M13 NC N2 NC A12 V C2 DV L12 HCNTL0 M3 V B11 SS DD SS DV C1 V L13 V N3 DV A11 DD SS SS DD A10 D4 CLKMD1 K10 BCLKR0 K4 D6 D10 HD7 D3 CLKMD2 K11 BCLKR1 L4 D7 C10 A11 D2 CLKMD3 K12 BFSR0 M4 D8 B10 A12 D1 NC K13 BFSR
ページ7に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 terminal functions The following table lists each signal, function, and operating mode(s) grouped by function. Terminal Functions TERMINAL TERMINAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME DATA SIGNALS A19 (MSB) O/Z Parallel address bus A19 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen A18 address pins (A0 to A15) are multiplexed to address all external m
ページ8に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Terminal Functions (Continued) TERMINAL TERMINAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME NAME INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED) Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the RS I CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects various
ページ9に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Terminal Functions (Continued) TERMINAL TERMINAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME NAME OSCILLATOR/TIMER SIGNALS Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle CLKOUT O/Z is bounded by rising edges of this signal. CLKOUT also goes into the high-impedance state when OFF is low. Clock mode select signals. These inputs select the mode t
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Terminal Functions (Continued) TERMINAL TERMINAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME NAME HOST-PORT INTERFACE SIGNALS (CONTINUED) Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup HBIL I resistor that is only enabled when HPIENA = 0. Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-se
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Terminal Functions (Continued) TERMINAL TERMINAL † † TYPE TYPE DESCRIPTION DESCRIPTION NAME NAME TEST PINS (CONTINUED) Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST EMU0 I/O/Z is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. Emulator 1 pi
ページ12に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory The ’5402 device provides both on-chip ROM and RAM memories to aid in system performance and integration. on-chip ROM with bootloader The ’5402 features a 4K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the ’5402 programmed with contents unique to any particular application. A security option is available to protect a custom ROM. This security option is described
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory map Page 0 Program Page 0 Program Data Hex Hex Hex 0000 0000 0000 Memory Reserved Reserved Mapped (OVLY = 1) (OVLY = 1) Registers 005F External External (OVLY = 0) 0060 (OVLY = 0) Scratch-Pad RAM 007F 007F 007F 0080 0080 0080 On-Chip DARAM On-Chip DARAM On-Chip DARAM (OVLY = 1) (OVLY = 1) (16K x 16-bit) External External (OVLY = 0) (OVLY = 0) 3FFF 3FFF 3FFF 4000 4000 4000 External External EFFF
ページ14に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 relocatable interrupt vector table (continued) 15 7654 3210 CLK IPTR MP/MC OVLY AVIS DROM SMUL SST OFF R/W R/W R/W R R R R/W R/W LEGEND: R = Read, W = Write Figure 2. Processor Mode Status (PMST) Registers extended program memory The ’5402 uses a paged extended memory scheme in program space to allow access of up to 1024K program memory locations. In order to implement this scheme, the ’5402 includes
ページ15に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 0 0000 1 0000 2 0000 F 0000 Page 1 Page 2 . . . Page 15 Lower Lower Lower 16K 16K . . . 16K 1 3FFF 2 3FFF F 3FFF External External External 2 4000 F 4000 1 4000 . . . Page 0 Page 1 Page 2 Page 15 64K Upper Upper Upper Words 48K 48K 48K External External External 2 FFFF F FFFF 0 FFFF 1 FFFF . . . † See Figure 1 ‡ The lower 16K words of pages 1 through 15 are available only when the OVLY bit is c
ページ16に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 on-chip peripherals The ’5402 device has the following peripherals: Software-programmable wait-state generator with programmable bank-switching wait states An enhanced 8-bit host-port interface (HPI8) Two multichannel buffered serial ports (McBSPs) Two hardware timers A clock generator with a phase-locked loop (PLL) A direct memory access (DMA) controller software-programmable wait-state
ページ17に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 software-programmable wait-state generator (continued) Table 2. Software Wait-State Register (SWWSR) Bit Fields BIT RESET RESET FUNCTION FUNCTION VALUE NO. NAME Extended program address control bit. XPA is used in conjunction with the program space fields 15 XPA 0 (bits 0 through 5) to select the address range for program space wait states. I/O space. The field value (0–7) corresponds to the base numb
ページ18に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 programmable bank-switching wait states The programmable bank-switching logic of the ’5402 is functionally equivalent to that of the ’548/’549 devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program or data memory space. A bank-switching wait state can also be automatically inserted when accesses cross the data space boundary into program space.
ページ19に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 parallel I/O ports The ’5402 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The ’5402 can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits. enhanced 8-bit host-port interface The ’5402 host-port interfa
ページ20に含まれる内容の要旨
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial ports The ’5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are based on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP provides: Full-duplex communication Double-buffe
