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Transistor Chip Use
Application Note A005
Part I. Assembly Considerations
1.0 Chip Packaging for Shipment
1.1 General
Hewlett-Packard transistor chips are shipped in chip carriers with a
clear or black elastomer as a carrier medium. There are up to 100 chips
in each pack. One of the corners of the pack is beveled to provide
orientation for chip selection.
1.2 Opening/inspection
Chip carriers should be opened only at a clean, well-lighted station
without fast-moving air. A white working surface i
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2 3.0 Die Attach Procedure Different die attach procedures are used for silicon chips and GaAs devices. To die attach a silicon chip, the chip and mounting surface are heated sufficiently for the gold of the mounting surface to mix with the gold backside of the chip and melt into the silicon of the chip, forming a gold-silicon eutectic bond. This technique is suitable because silicon can tolerate the relatively high temperatures needed for eutectic formation without endangering the silicon devic
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3 3.2.4 Pick up a chip with tweezers (EREM type 5 SA recommended) and orient it properly prior to placement on the heated surface. 3.2.5 Place the chip on the heated surface and scrub with a back-and- forth motion being careful not to scratch the top surface of the chip. Continue this until wetting occurs; this should take place within 3 to 4 scrubs. 3.2.6 If wetting does not occur check that the heater block temperature is correct and that the inert atmosphere blanket is present. 3.2.7 When
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4 4.2 Thermocompression Wedge Bonding In circuits where there is good access to the transistor chip bonding pads and to the circuit elements to which the chip bonds run, a variety of wedge bonders, including many new semi-automatic units, can be used. In situations where horizontal access is very limited (such as a transistor package), a manual machine with a small chisel wedge may be the most appropriate. The wedge does not have to be heated, but if it is the heater block temperature may be lo
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5 6.0 Electrostatic Discharge Precautions The following discussion applies mainly to GaAs FET devices, but excess voltages can damage a silicon bipolar device as well. Slight degradation of a GaAs FET device can occur with electrostatic potentials as low as 500 volts and capacitances on the order of that of the human body. Unfortunately, it is very easy to generate static charge of this magnitude through the motion of an arm, by sliding plastic objects together, or by the motion of the body on a
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used. The S-parameter data, as presented in HP chip transistor data sheets, includes the bond wire inductance (approximately 0.7 nH per wire), microstrip line end-effect capacitance (about 0.02 pF) and microstrip line losses (about 0.1 dB). A designer modeling the chip should adjust these parasitic elements appropriately for the specific circuit configuration. Bipolar transistor chips are characterized in a slightly different configuration because the substrate/backside of the chip is the collec
