ページ1に含まれる内容の要旨
MZ-3500
SERVICE MANUAL
CODE: OOZMZ 3500SM/E
PERSONAL COMPUTER
Z-350
MODEL
CONTENTS
1. Specifications 1
2. Software (Memory) Configuration 7
3. CPU and memory 12
4. CRT display 25
5. MFD interface 52
6. R232C interface 72
7. Printer interface yg
8. Other interface 81
9. Power circuit description gy
10. Keyboard controller circuit discription 90
11. Self check functions 94
12. IPL flow chart 103
13. Circuit diagram & P.W.B
Parts list & Guide
SHARP CORPORATION
ページ2に含まれる内容の要旨
M 7 3500 1. SPECIFICATIONS 1-1. Specification of the main unit (Model 35XX ) 1) High speed processing using multi-CPL' 2) Built in mini floppy disk 3) Built in printer interface and RS232C Aerial interface Outline 4) Connection of up to two video displa, mitt (separate graphic display or overlaid display possible on two individual color monitor units) 5) Permits the use of standard CP/M Model 3530 incluse a single double-side, double density mini floppy Model 3531 includes a single double side,
ページ3に含まれる内容の要旨
MZ3500 1-2. MZ-1K01 (Keyboard) specification MZ1K02 U.S. keyboard (ASCII) MZ1K03: U.K. keyboard (ISO). Outline MZ1K04 German keyboard MZ1K05: French keyboard Keyboard controller 80C49 or 8749 LSI, 1C CMOSIC 4049x2,4514 Sculpture key Mechanical contact key, with life of 10,000,000 operations. Keys (98) Alphanumeric keys 61 Ten key 15 Function keys 6 Definable keys 10 Mode switch 1 For data transfer with the CPU (serial) and power supply (transmission under 15,000 baud) Interfacing cables Specific
ページ4に含まれる内容の要旨
MZ3500 Expansion unit Screw (1) 1-4. MZ-IR03 Optional board used graphic display functions with the Model-3500 series CPU. It includes 32KB of RAM. Outline It is inserted through the slot on the front panel of the PU. The MZ-1U02 expansion box is not required. GDC Graphic controller MPD7220 LSI Basic (buit-in) 16KDRAM x 16 (32KB) vinrn HAM Expansion 16KORAM x 32 (64KB) (optional) Specifications ~~~~~ — ____WDE O RAM 32KB 96KB (basic) (maximum expansion) Graphic functions 640 x 200 640 x 200 dots
ページ5に含まれる内容の要旨
MZ3500 1-6. MZ-1R06 Optional board for memory expantion of the MZ-3500 sries CPU. with this option the main memory (RAM) can be expanded up to a maximum of 256 KB. Outline This option plug into the expantion box in slot 1 or 3. Basic 64KDRAM x8 (64KBI LSI Expansion 64KDRAM x8 (128KB) Specifications Memory and user Using eight 64K RAM's Main CPU only Use of MZ-1R06 area on theMZ-1R06 Total capacity of 128 KB 192 KB 256KB the main CPU RAM SYSTEM • 57 KB «- *- : AREA BASIC (RAM USER BASE 80 KB 128
ページ6に含まれる内容の要旨
MZ3500 1-7. MZ-1D07 High resolution MZ 3500 series 12 green Outline monitor Non glare green Type Size 12", 90" deflection Video tube Fluorescent color P39 (green, long PERSISTANCE) Total number of 2,000 characters 640 horizontal dots, Display capacity Display capacity display characters (80 characters x 25 lines) 400 vertical lines Specifications Display size 220 x 145 Method Separate input, TTL level Input signals Horizontal 20 86kHz Vertical 47 8 Hz Power supply 29W power consumpt ion Color Mo
ページ7に含まれる内容の要旨
MZ3500 1-8. System configuration of Model 3500 Keyboard MZ-1K02 MZ-1K03 MZ-1K04 MZ-1K05 Printer ' IO2824E I I I Option MFDI I CE-331M | I I "Model-3541 = Model-3531 + MZ-1F03 6
ページ8に含まれる内容の要旨
MZ3500 2. SOFTWARE (MEMORY) CONFIGURATION Memory will be operated under four states of SDO ~ SD3, 2-1. SDO (INITIALIZ E STATE) depending on the hardware and software configurations. SDO can only exist immediately after power on, and the In the paragraphs to follow, description will be made for system executes IPL under this condition and that the those four states. system thus loaded will automatically assign memory area for SD1, SD2. and SD3. MAIN CPU SUB CPU MAS 0 0 1 MA2 0 0 1 MAI 0 0 1 MS1 =
ページ9に含まれる内容の要旨
M 7. 3500 Operational description (1) Upon reset after power on, the main CPU loads the (2) The main CPU then terminates resetting the sub CPU contents of the initial program loader (IPL) into RAM and starts the sub-CPU. At the same time, the ROM starting at address 4000H, during which time reset is IPL is assigned to the sub-CPU. applied to the sub-CPU. (3) The main CPU then send the memory allocation (state) to SD1, and starts to load DOS from the system floppy disk. TIMING OF RESET SIGNAL Vtc
ページ10に含まれる内容の要旨
MZ3500 ROM-IPL Mam CPU logical address (during IPL operation) 1. An 8KB ROM (2764 or mask ROM equivalent) is used Logical address of the sub-CPU for the ROM-IPL. ROM physical address 2. When the system reset signal turns from low to high state after power on, the main CPU starts to operate At OfFF this stage, the ROM-IPL is addressed. 1 FFF 1 FFF 3. The CPU starts from address OOOOIROM address 10000) 4. The main CPU sets the sub-CPU reset signal from low to high state as it goes out of its initi
ページ11に含まれる内容の要旨
MZ3500 Operational description (1) As soon as the sub-CPU is started, it initializes the I/O "1" of track "0" of the floppy disk, it loads the IOCS port and waits for program transfer (IOCS) from the and bootstrap routine to the sub-CPU. main CPU. This IOCS (Input Output Control System) (3) The bootstrap program is loaded next. is the program resident at address 4000H-5FFFH. (4) The bootstrap program determines rnemory allocation. (2) As the main CPU loads the information from sector Communicati
ページ12に含まれる内容の要旨
MZ3500 2-4. SD3 (RAM based BASIC) SD3 is active when "SHARP BASIC" is ececuted via RAM. "SHARP BASIC" is loaded in RAM from the floppy disk. MSI = 1< H ) MAIN CPU MSO = HH) SUB CPU MAS 000 0 000 0 III ! 1 RAM MA2 000 0 111 1 000 0 1 BANK MAI 001 1 001 ) 001 1 1 SELECT MAO 010 1 010 1 010 1 1 Ffft II I III III lRwnuf r 1 % \\ \ RAMB RANC KAMI) \ v \v 1 2,3, 4 1,2,3,4 1,2,3,4 \\ gFFF \\ N\ vx - \\ RAN. SP \\ RAN SC , \ , RAM SB KU "° RAMA ROM! ROM2 KOM3 K(IM4 \\ ROM BAS 1FFF k ' SUB CPU ROM 1 PI
ページ13に含まれる内容の要旨
3. CPU AND MEMORY 3-1. Block diagram 1) Relation between MMR (Main Memory Mapper) and main memory. I RECE I VF R , RAM I (II'TION 1 1 RAN 4- VI ° l ' 64KBV2) OPTION 1 . || '7220 I i (, ,APM,C JK» 2K* J MPXR {) R VIIIK1 RAM 32K B V 1 HI O RAM 32K B It VIDH) RAM 32K H Ml DM1 I MO*J L OK II K U MO* 400 kl Mil I 1 ION RS-232C l/f si v i (.us TOM 1 SI CSI -2 SEMI CUSTOM IS! CSI'-I
ページ14に含まれる内容の要旨
MZ3500 3-2. Main CPU and I/O port This paragraph discusses main CPU I/O Connector Port select and addressing. I PC 2 The address output from the main CPU A2 |~^T 1 is decoded in the 74LS138 to create the r^ "" v select signal. IX A3 j^ ~s f^-r-^r-. — r Table below describes address map and Y 1 ~~> \J> -•> r DL M A4 signal functions. A iZ J \J I Obr I —££-1 N A6 A v~\ r (jtA. Y3 M P C C -) f\ J -\J Y4 P IORQ G2 B u Y5 ^ 0 MFUC M i Ol Y6 • \J lUMr 5 O IOABCMEMORY MAPPER) 74LSI38 ADDRESS A7 A6 A5 A
ページ15に含まれる内容の要旨
MZ3500 3-3. Sub CPU and I/O port Shown at the left is the circuit used by the CPU to select the I/O ports The out J s07 *. AS6 5 put address from the sub CPU is decoded ~9 S06 by the 74LS138to create the select signal. Y6 ASS 2 Shown below is the address map and _JQ SOS ^ J r CKP 1 . CSP 2 SUB AS4 i select signals. .Jl SO4 ^ . . ...... CPU 4G Y4 AST 4_ 12 S03 ,. -^ 0 *"" 5 D15 S°2 HEC3 -C* "MT 14 "SOT -^ 6 Gl Yl D15 '*°° r MAIN CPU \m YO 74LS138 8 8 8 Signal description 8 1 23456789ABCDE F AS
ページ16に含まれる内容の要旨
MZ3500 3-4. Memory mapper (MMR) SP6102R-001 1) Block diagram Memory mapping logic A 15 A15 A14 AU AI3 ADDRESS BUS A] AO . i . is. AO COAB COAB MKEQB RFSH ~L I/ O CONTROL BUS - PORT MERQ RB — L LOGIC RFSH RD "WR OAB n DATA BUS I — \ DO-D7 V INTB WAIT TIMING WAITB GENERATOR INTERRUPT PRIORITY ENCORDER CLK ->TO RESET SYSR 1NTFI ) - 19 -
ページ17に含まれる内容の要旨
MZ3500 2) Memory mapper (MMR) SP6102R-001 signal description Polarity Signal Name 1 ST IN Main CPU DRAM output buffer (LS244) switching strap. DO 2 Bidirectional main CPU data bus. IN/OUT (Data bus 0 ~ 7) 9 D7 A15 10 Main CPU address bus. IN Used in the memory mapping logic of the MMR for address output for the DRAM, ROM, and A13 shared RAM. (Address bus 13 ~ 15) 12 Main CPU address bus. 13 A1 IN Used in the I/O port select logic of the MMR to assign device number. Sub-CPU bus request signal. •
ページ18に含まれる内容の要旨
M 7, 3500 Polarity IN/OUT Function Pin No. Signal Name Main CPU 128KB dynamic RAM output buffer (LS244) output enable signal. OUT 32 RF1B (RAM buffer 1) Signal identical to R F 1 B For option RAM RF2B OUT 33 (RAM buffer 2) Wait signal to the mam CPU OUT (One wait cycle 15 applied during the memory fetch cycle of the main CPU. It consists of one clock 34 WATB period) (WA|T) Chip select signal issued from the mam CPU to select the RAM shared by the main CPU and OUT 35 RCMB the sub-CPU (RAM Common
ページ19に含まれる内容の要旨
MX 3500 Polarity Pin No IN/OUT Function Signal Name System reset signal. 57 SYSR IN Used to reset I/O port in the MMR. (System Reset) Input from the sytem assignment dip switch. FD3 IN 58 "See the dip switch description, provided separately. Shared RAM select signal. 59 COAB IN Address of the shared RAM is *F800-#FFFF for the main CPU (Common RAM Address) Select signal for 8KB area allocated to slot 1. 60 RO1B OUT Valid when SD2 is active (ROM based BASIC) and SD3 (RAM based BASIC) (ROM 1) Groun
ページ20に含まれる内容の要旨
M 7.3500 MAIN CPU I/O PORT IN MEMORY MAPPER ADDKKSS UHUS A7 A6 A5|A4|A3|A2|Al|AO HE X 1 O 01 SKQB SRQ Bus request fro m the mam CPU to the sob-CPU r\i IT DO 1 1 D7 SKI S Sub-CPU reset signal Dl MS ] KI) 1 1 1 1 1 1 0 1 Memory system define DO MS O 1)7 M<\3 Bank select signal to memory area of COOO-FFFF. D6 MA2 D5 MA I D4 OUT MA O _J D2 MO2 Bank select signal to memory area of 2000-3FFF. Dl MO I FE DO MOO 1111111 0 D4 SW 4 D3 b«3 System assign switch D2 INI M\2 Dl Sttl DO she D7 FD3 FD assign D6
