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LogiCORE™
PCI v3.0
Getting Started Guide
UG157 August 31, 2005
v3.0.151
R
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R Xilinx is disclosing this Specification to you solely for use in the development of designs to operate on Xilinx FPGAs. Except as stated herein, none of the Specification may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of this Specification may violate cop
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Version Revision 06/24/02 3.0 Initial Xilinx release of corporate-wide common template set, used for User Guides, Tutorials, Release Notes, Manuals, and other lengthy, multiple-chapter documents created by both CMP and ITP. See related documents for further information. Descriptions for revisions prior to v3.0 have been abbreviated. For a full summary of revision changes prior to v3.0, refer to v2.2.1 template set. 10/30/02 3.1 Updated spelling of RocketIO and SelectIO trademarks in ug000_tit
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PCI v3.0.151 Getting Started Guide www.xilinx.com UG157 August 31, 2005
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Table of Contents Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 5: Synthesizing a Design Synplicity Synplify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Exemplar LeonardoSpectrum . . . . . . . . . . . . . . .
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R Preface About This Guide The PCI Getting Started Guide provides information about the LogiCORE™ Peripheral Component Interconnect (PCI) interface, which provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions. This guide discusses the supported design flows for 32-bit and 64-bit PCI interfaces based on the Virtex™ and Spartan™ architectures, and provides an example design in both Verilog-HDL and VHDL. Guide Contents This manual contains th
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R Preface: About This Guide Additional Resources For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs. Resource Description/URL Tutorials Tutorials covering Xilinx design flows, from design entry to verification and debugging http://support.xilinx.com/support/techsup/tutorials/index.htm Answer Browser Database of Xilinx solution records
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R Conventions Convention Meaning or Use Example Variables in a syntax statement for which you must ngdbuild design_name supply values See the Development References to other manuals System Reference Guide Italic font for more information. If a wire is drawn so that it overlaps the pin of a symbol, Emphasis in text the two nets are not connected. An optional entry or parameter. However, in bus ngdbuild [option_name] Square brackets [ ] specifications, such as design_name bus[7:0], the
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R Preface: About This Guide 10 www.xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005
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R Chapter 1 Getting Started The PCI interface provides a fully verified, pre-implemented PCI bus interface available in both 32-bit and 64-bit versions with support for operation at 33 MHz and 66 MHz. This guide defines the supported design flows for both the 32-bit and 64-bit interfaces targeting devices based on the Virtex and Spartan architectures. In addition, an example design is provided in both Verilog-HDL and VHDL that lets you simulate, synthesize, and implement the interface to un
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R Chapter 1: Getting Started Technical Support For technical support, visit www.xilinx.com/support. Questions are routed to a team of engineers with expertise using the PCI interface. Xilinx provides technical support for use of this product as described in the PCI User Guide and the PCI Getting Started Guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs that do not follow these guidelines. Feedback Xilinx welcomes comments and suggestions about the PC
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R Chapter 2 Installing and Licensing the Core This chapter provides instructions for installing and obtaining a license for the PCI interface core, which you must do before using it in your designs. The PCI core is provided under the terms of the Xilinx LogiCORE Site License Agreement or the Xilinx LogiCORE Project License Agreement, which conform to the terms of the SignOnce IP License/Project standard defined by the Common License Consortium. Purchase of the PCI core entitles you to techn
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R Chapter 2: Installing and Licensing the Core CORE Generator IP Updates Installer 1. From the CORE Generator main GUI, choose Tools > Updates Installer to start the Updates Installer. 2. If prompted for a proxy host, contact your administrator to determine the proxy host address and port number you need to get through your firewall. 3. Select 7.1i_IP_Update3 from the list of updates in the Available Packages panel. 4. Click Add To Install Queue to add the update ZIP file to the install que
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R Installing the Core the location of the Xilinx installation. Note that you may need system administrator privileges to install the update. 6. Confirm the directory structure in one of the following ways: For Windows: \coregen\ip\xilinx\network_ip1_h\com\xilinx \ip\pci64_v30151 For UNIX: /coregen/ip/xilinx/network_ip1_h/com/xilinx /ip/pci64_v30151 If you do not see this directory structure, recheck the directory to which you extracted the
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R Chapter 2: Installing and Licensing the Core Licensing Options Evaluation The method for obtaining an evaluation license is determined by the version of the PCI core you choose. • For the PCI32/33 Virtex™ and Spartan™ core, register on the Xilinx IP Evaluation page at www.xilinx.com/ipcenter/ipevaluation. From this location, access is granted and you can generate your own license. • For the PCI 64/66 core, please contact your locate FAE to request a Full System Hardware Evaluation licens
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R Installing Your License File Installing Your License File After selecting a license option, an email will be sent to you that includes instructions for installing your license file. In addition, information about advanced licensing options and technical support is provided. PCI v3.0.151 Getting Started Guide www.xilinx.com 17 UG157 August 31, 2005
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R Chapter 2: Installing and Licensing the Core 18 www.xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005
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R Chapter 3 Family Specific Considerations This chapter provides important design information specific to the PCI interface targeting Virtex and Spartan devices. Design Support Table 3-1 provides a list of supported device and interface combinations. Each entry in the table consists of a device, a bus interface type, and two or three specific implementation files. Table 3-1: Device and Interface Selection Table Supported Bus Constraints File/ Wrapper File Device Type Guide File 2S100-FG456-6
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R Chapter 3: Family Specific Considerations Table 3-1: Device and Interface Selection Table (Continued) Supported Bus Constraints File/ Wrapper File Device Type Guide File 2S200-FG456-6C 33 MHz pcim_lc_33_3_s 2s200fg456_64_33.ucf 3.3V no guide file 64-bit 2S200-FG456-6C 66 MHz pcim_lc_66_3_d 2s200fg456_64_66.ucf 3.3V 2s200fg456_64_66.ncd 64-bit 2S100E-FG456-6C 33 MHz pcim_lc_33_3_s 2s100efg456_64_33.ucf 3.3V no guide file 64-bit 2S150E-FG456-6C 33 MHz pcim_lc_33_3_s 2s150efg456_64_33.ucf 3.3V no
