B&B Electronics 2IQEC4の取扱説明書

デバイスB&B Electronics 2IQEC4の取扱説明書

デバイス: B&B Electronics 2IQEC4
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メーカー: B&B Electronics
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追加した日付: 4/9/2014
ページ数: 22
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内容要旨
ページ1に含まれる内容の要旨

Quadrature Encoder Counter Board
Models: 2IQEC2 2IQEC4
Documentation Number 2IQEC2/43798
This product
Designed and Manufactured
In Ottawa, Illinois
USA
of domestic and imported parts by
B&B Electronics Mfg. Co. Inc.
707 Dayton Rd. P.O. Box 1040 -- Ottawa, IL 61350
PH (815) 433-5100 -- FAX (815) 433-5105
Internet:
http://www.bb-elec.com
orders@bb-elec.com
support@bb.elec.com







 1998 B&B Electronics -- September 1998
2IQEC2/43798 Manual Cover Page
B&B Electronics -- PO Box 1040 -- Ott

ページ2に含まれる内容の要旨

Table of Contents CHAPTER 1: INTRODUCTION............................................................ 1 PACKING LIST........................................................................................... 1 ADDRESS SWITCH SETUP.......................................................................... 1 SPECIFICATIONS........................................................................................ 2 CHAPTER 2: INSTALLATION ..........................................................

ページ3に含まれる内容の要旨

Chapter 1: Introduction The 2IQEC2/4 is a 2/4 channel quadrature encoder 24 bit counter card used to track the position of up to 4 separate encoders. This card is an ISA card that can be used in either an 8 or 16 bit slot. This card allows the computer to keep track of position without a lot of CPU overhead, freeing it up for more important tasks. The 2IQEC2/4 offers a huge amount of flexibility. Upon a borrow or carry the card can be configured to reset, load a preset, cause an interrupt reques

ページ4に含まれる内容の要旨

Specifications Bus: IBM PC ISA Bus Slot: Requires 1 full length slot for complete IRQ selectability. When installed in a short slot, IRQs 10-15 will not be available. The four channel card requires an additional space to mount the connectors in the back panel. This space does not need a slot on the motherboard. Dimensions: 8.75" x 4.4" I/O connection: 15-pin female D-sub connectors Interrupt: IRQ 2-7, 10-12, 14, or 15. Address: Switch programmable, 0 to hex 7F0 RS-422 Differential inputs

ページ5に含まれる内容の要旨

Chapter 2: Installation Software Installation The 2IQEC2/4 comes with a useful example program. This example program may be used royalty free when used with the B&B Electronics 2IQEC2/4. Any other use is strictly prohibited. To install this example file on your hard drive: 1. Place the disk in drive A: 2. Type A: and press the key. 3. Type Install and press the key. 4. Follow the instructions given by the program. Installing the Card 1. Turn the power to your computer off. 2. Rem

ページ6に含まれる内容の要旨

Table 1. Address Switches 1st Digit 2nd Digit Switch 7 6 54321 Position SA10 SA9 SA8 SA7 SA6 SA5 SA4 Bus Connection 1024 512 256 128 64 32 16 Decimal Weight 400 200 100 80 40 20 10 Hex Weight To set the address of the 2IQEC2/4 card at some common locations, follow the switch settings shown in Table 2. Table 2. Frequently Unused Port Addresses Base Binary Switch I/O Space Hex Equivalent Settings Description MSB LSB Address 7654321 200 1000000000 0100000 game port 300 1100000000 0110000 prototype

ページ7に含まれる内容の要旨

IRQ The 2IQEC2/4 card allows the use of interrupts (IRQ) 2-7, 10-12, 14, and 15. This interrupt is shared with all the channels. To determine the channel that caused the interrupt, the interrupt service routine must read the address located at the base address plus 8. The lower nibble will indicate which channel caused the interrupt. Where bit 0 is the X-Axis, bit 1 is the Y-Axis, bit 2 is the Z- Axis, and bit 3 is the W-Axis. The upper nibble is not used. To clear the interrupt, the interrupt s

ページ8に含まれる内容の要旨

Configuring the jumpers The jumpers located on the left side of the card make it easy to configure the card to your individual needs. The jumpers are grouped by axis and function. The top group of jumpers is for the X axis. Then next groups going down are for the Y-axis, Z-axis, and W-axis respectfully. There are three signals that can be routed via these jumpers. They are the FLG1 and FLG2 outputs from the counter chips, and the index from the encoder. The FLG1 and FLG2 outputs are software con

ページ9に含まれる内容の要旨

Location of Jumpers 2IQEC2/43798 Manual 7 B&B Electronics -- PO Box 1040 -- Ottawa, IL 61350 PH (815) 433-5100 -- FAX (815) 433-5105

ページ10に含まれる内容の要旨

Software Registers Flag Register (Read Data Address) The FLAG register is a read-only register that holds the status information of the counters and can be read out on the data bus. To read the FLAG byte for any axis, read the control address of that axis. FLAG Byte Defined 76543210 BT: Borrow toggle flip-flop. Toggles every time CNTR underflows CT: Carry toggle flip-flop. Toggles every time CNTR overflows CPT: Compare toggle flip-flop. Toggles every time PR equals CNTR. S: Sign flag. Set to 1 w

ページ11に含まれる内容の要旨

Filter Clock Prescalers Each PSC is an 8-bit programmable modulo-N down counter, driven by the FCK clock. The factor N is downloaded into a PSC from the associated PR low byte register PR0. The PSCs provide the ability to generate independent filter clock frequencies for each channel. Final filter clock frequency FFCKn=fFCK/(n+1), where n=PSC=0 to 255 Counter Mode Registers (Write to Control Address) The counter’s operational mode is programmed by writing a byte into the counter mode registers (

ページ12に含まれる内容の要旨

Non-Recycle. In non-recycle count mode, the CNTR is disabled, whenever a count overflow or underflow takes place. The end of cycle is marked by the generation of a Carry (in Up Count) or a Borrow (in Down Count). The CNTR is re-enabled when a reset or load operation is performed on the CNTR. Modulo-N. In modulo-N count mode, a count boundary is set between 0 and the content of PR. When counting up at CNTR=PR, the CNTR is reset to 0 and the up count is continued from that point. When counting dow

ページ13に含まれる内容の要旨

Index Control Registers (Write to Control Address) Either the LCNTR'/LOL' or the RCNTR'/ABG inputs can be initialized to operate as an index input. When initialized as such, the index signal from the encoder, applied to one of these inputs performs either the Reset CNTR or the Load CNTR or the Load OL operation synchronously with the quadrature clocks. Note that only one of these inputs can be selected as the Index input at a time and hence only one type on indexing function can be performed in

ページ14に含まれる内容の要旨

Chapter 3: TROUBLESHOOTING If you are unable to communicate with the card from your software: 1. Double check that the address is properly set. 3. Check your pinouts. 4. Try the demo software that comes with the card. 5. Call B&B Electronics' Technical Support. Technicians are available at (815) 433-5100 to answer your questions from 8 am - 5:00 pm weekdays (Central Time). 12 2IQEC2/43798 Manual B&B Electronics -- PO Box 1040 -- Ottawa, IL 61350 PH (815) 433-5100 -- FAX (815) 433-5105

ページ15に含まれる内容の要旨

Appendix A: Hardware I/O Map I/O Map of XT Class Machines Hex Address Address Function in XT Class Machines 000-00F DMA controller (8237A) 020-021 interrupt controller (8259A) 040-043 timer (8253) 060-063 PPI (8255A) 080-083 DMA page register (74LS612) 0A0-0AF NMI - non maskable interrupt 200-20F game port joystick controller 210-217 expansion unit 2E8-2EF COM4 serial port 2F8-2FF COM2 serial port 300-31F prototype card 320-32F hard disk 378-37F parallel printer 380-38F SDLC 3B0-3BF MDA - monoch

ページ16に含まれる内容の要旨

Hardware I/O Map of AT Class Machines Hex Address Address Function in AT Class Machines 000-01F DMA controller #1 (8237A-5) 020-03F interrupt controller #1 (8259A) 040-05F timer (8254) 060-06F keyboard (8042) 070-07F NMI - non maskable interrupt & CMOS RAM 080-09F DMA page register (74LS612) 0A0-0BF interrupt controller #2 (8259A) 0C0-0DF DMA controller #2 (8237A) 0F0-0FF 80287 math coprocessor 1F0-1F8 hard disk 200-20F game port joystick controller 258-25F Intel Above Board 278-27F parallel pri

ページ17に含まれる内容の要旨

Appendix B: Specifications/Timing Diagrams Pin Description 1. A+ 2. A- 3. A (TTL) 4. B+ 5. B- 6. B (TTL) 7. I+ 8. I- 9. I (TTL) 10. FLG 2 (Programmed output) 11. FLG 1 (Programmed output) 12. Load Counter (Input) 13. Reset Counter (Input) 14. +5VDC 15. Ground Addresses Base ............................. X Axis Data Base+1 ......................... X Axis Control Base+2 ......................... Y Axis Data Base+3 ......................... Y Axis Control Base+4 ......................... Z Axis Da

ページ18に含まれる内容の要旨

Transient Characteristics Quadrature Mode Parameter Symbol Min.Value Max. Value Unit Remarks FCK High Pulse Width t1 21 - ns - FCK Low Pulse Width t2 21 - ns - FCK Frequency fFCK -24 MHz- Mod-n FilterClock(FCKn)Period t 3 42 - ns t3= (n+1) (t1+t2), where N=PSC=0 to FFH FCKn Frequency fFCKn -24 MHz- Quadrature Separation t4 83 - ns t4≥2t3 Quadrature ClockPulse Width t 5 167 - ns t5≥4t3 Quadrature ClockFrequency f QA,fQB-3 MHzfQA=fQB=1/8t3 Quadrature Clockto CountDelay t Q1 5t3 6t3 -- X1/X2/X4

ページ19に含まれる内容の要旨

Filter Clock (modulo-1 shown) Quadrature Clock and Index (Positive index shown) 2IQEC2/43798 Manual Appendix B: Specifications B-3 B&B Electronics -- PO Box 1040 -- Ottawa, IL 61350 PH (815) 433-5100 -- FAX (815) 433-5105

ページ20に含まれる内容の要旨

Carry, Borrow, Compare, Carry Toggle, Borrow Toggle and Compare Toggle (4X Quadrature, Normal, Binary Count, and PR=1) Non Quadrature mode (A=Count B=Direction) B-4 Appendix B: Specifications 2IQEC2/43798 Manual B&B Electronics -- PO Box 1040 -- Ottawa, IL 61350 PH (815) 433-5100 -- FAX (815) 433-5105


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