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S3F80JB
8-BIT CMOS
MICROCONTROLLERS
USER'S MANUAL
Revision 1.1
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Important Notice The information in this publication has been carefully "Typical" parameters can and do vary in different checked and is believed to be entirely accurate at applications. All operating parameters, including the time of publication. Samsung assumes no "Typicals" must be validated for each customer responsibility, however, for possible errors or application by the customer's technical experts. omissions, or for any consequences resulting from Samsung products are not designe
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Preface The S3F80JB Microcontroller User's Manual is designed for application designers and programmers who are using S3F80JB microcontroller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters: Chapter 1 Product Overview Chapter 4 Cont
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Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8/S3F8-Series Microcontrollers ...........................................................................................................1-1 S3F80JB Microcontroller ............................................................................................................................1-1 Features ....................................................................................................................
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Table of Contents (Continued) Chapter 5 Interrupt Structure Overview ....................................................................................................................................................5-1 Interrupt Types...................................................................................................................................5-2 Interrupt Vector Addresses................................................................................................
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Table of Contents (Continued) Chapter 8 RESET Overview ....................................................................................................................................................8-1 Reset Sources ...................................................................................................................................8-1 Reset Mechanism ..........................................................................................................................
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Table of Contents (Continued) Chapter 10 Basic Timer and Timer 0 Overview ....................................................................................................................................................10-1 Basic Timer (BT) ................................................................................................................................10-1 Timer 0.............................................................................................................
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Table of Contents (Continued) Chapter 15 Embedded Flash Memory Interface Overview ....................................................................................................................................................15-1 TM ISP (On-Board Programming) Sector.....................................................................................................15-3 ISP Reset Vector and ISP Sector Size..................................................................................
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List of Figures Figure Title Page Number Number 1-1 Block Diagram (32-pin).............................................................................................1-3 1-2 Block Diagram (44-pin).............................................................................................1-4 1-3 Pin Assignment Diagram (32-Pin SOP Package) .....................................................1-5 1-4 Pin Assignment Diagram (44-Pin QFP Package)..........................................
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List of Figures (Continued) Figure Title Page Number Number 5-1 S3C8/S3F8-Series Interrupt Types...........................................................................5-2 5-2 S3F80JB Interrupt Structure.....................................................................................5-4 5-3 ROM Vector Address Area.......................................................................................5-5 5-4 Interrupt Function Diagram...............................................
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List of Figures (Continued) Figure Title Page Number Number 12-1 Counter A Block Diagram .........................................................................................12-2 12-2 Counter A Control Register (CACON) ......................................................................12-3 12-3 Counter A Registers .................................................................................................12-3 12-4 Counter A Output Flip-Flop Waveforms in Repeat Mode........
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List of Figures (Continued) Figure Title Page Number Number 18-1 Typical Low-Side Driver (Sink) Characteristics (P3.1 only)·······································18-5 18-2 Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3)·························18-5 18-3 Typical Low-Side Driver (Sink) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) ··························································18-6 18-4 Typical High-Side Driver (Source) Characteristics (P
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List of Tables Table Title Page Number Number 1-1 Pin Descriptions of 32-SOP......................................................................................1-7 1-2 Pin Descriptions of 44-QFP......................................................................................1-8 2-1 S3F80JB Register Type Summary ...........................................................................2-5 4-1 Mapped Registers (Bank0, Set1) ....................................................
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List of Tables (Continued) Table Title Page Number Number 15-1 Descriptions of Pins Used to Read/Write the Flash in Tool Program Mode ..............15-2 15-2 ISP Sector Size ........................................................................................................15-5 15-3 Reset Vector Address...............................................................................................15-5 17-1 Absolute Maximum Ratings................................................
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List of Programming Tips Description Page Number Chapter 2 Address Spaces Setting the Register Pointers......................................................................................................................2-11 Using the RPs to Calculate the Sum of a Series of Registers.....................................................................2-12 Addressing the Common Working Register Area .......................................................................................2-
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List of Register Descriptions Register Full Register Name Page Identifier Number BTCON Basic Timer Control Register....................................................................................4-5 CACON Counter A Control Register ......................................................................................4-6 CLKCON System Clock Control Register.................................................................................4-7 CMOD Comparator Mode Register..................
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List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADC Add with carry..........................................................................................................6-14 ADD Add...........................................................................................................................6-15 AND Logical AND.............................................................................................................6-16 BAND Bit AND....
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List of Instruction Descriptions (Continued) Instruction Full Register Name Page Mnemonic Number NEXT Next..........................................................................................................................6-60 NOP No Operation............................................................................................................6-61 OR Logical OR................................................................................................................6-62
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S3F80JB PRODUCT OVERVIEW 1 PRODUCT OVERVIEW S3C8/S3F8-SERIES MICROCONTROLLERS Samsung's S3C8/S3F8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various flash memory ROM sizes. Important CPU features include: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupts — Built-in basic timer with watchdog function A sophisticated interrupt s
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PRODUCT OVERVIEW S3F80JB FEATURES CPU Basic Timer and Timer/Counters • One programmable 8-bit basic timer (BT) for • SAM8 RC CPU core oscillation stabilization control or watchdog timer Memory (software reset) function • Program memory: • One 8-bit timer/counter (Timer 0) with three - 64-Kbyte Internal Flash Memory operating modes: Interval mode, Capture and - Sector size: 128Bytes PWM mode. - 10years data retention • One 16-bit timer/counter (Timer1) with two - Fast Programming
