ページ1に含まれる内容の要旨
INTEGRATED CIRCUITS
DATA SHEET
SAA7345
CMOS digital decoding IC with
RAM for Compact Disc
1998 Feb 16
Product specification
Supersedes data of 1996 Jan 09
File under Integrated Circuits, IC01
ページ2に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc FEATURES GENERAL DESCRIPTION • Integrated data slicer and clock regenerator The SAA7345 incorporates the CD signal processing functions of decoding and digital filtering. The device is • Digital Phase-Locked Loop (PLL) equipped with on-board SRAM and includes additional • Demodulator and Eight-to-Fourteen Modulation (EFM) features to reduce the processing required in the analog decoding domain.
ページ3に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc BLOCK DIAGRAM V V V V V V DD1 DD2 DDA SSA SS1 SS2 11 12 15 16 44 43 HFIN 8 22 MOTO1 DIGITAL MOTOR PLL HFREF 9 CONTROL 23 MOTO2 PLL FRONT- ISLICE 7 END EFM IREF 10 ERROR DEMODULATOR CORRECTOR TEST1 6 33 CFLG FLAGS TEST2 5 SRAM 13 CRIN AUDIO PROCESSOR CROUT 14 CL11 1 RAM TIMING ADDRESSER SAA7345 EBU CLA 29 2 DOBM INTER- FACE CL16 17 Q - CHANNEL CRC CHECK 21 SCLK PEAK Q - CHANNEL CL 31 REGISTER DE
ページ4に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc PINNING SYMBOL PIN DESCRIPTION CL11 1 11.2896 or 5.6448 MHz clock output (3-state); (divide-by-3) DOBM 2 bi-phase mark output (externally buffered; 3-state) V1 3 versatile input pin V2 4 versatile input pin TEST2 5 test input; this pin should be tied LOW TEST1 6 test input; this pin should be tied LOW ISLICE 7 current feedback output from data slicer HFIN 8 comparator signal input HFREF 9 compa
ページ5に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc Pins 34 to 42 (inclusive) have no internal connection CL11 1 33 CFLG 32 DOBM 2 RAB V1 3 31 CL 4 V2 30 DA TEST2 5 29 CLA 6 TEST1 28 PORE SAA7345 ISLICE 7 27 KILL HFIN 8 26 V3 HFREF 9 25 V4 IREF 10 24 V5 V 11 23 MOTO2 DDA MGA359 - 1 Fig.2 Pin configuration. 1998 Feb 16 5 V SSA 12 44 V DD2 13 43 V CRIN SS2 CROUT 14 42 V 41 DD1 15 V 16 40 SS1 CL16 17 39 18 38 MISC 19 37 DATA 20 36 WCLK 21 35 SCLK
ページ6に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc FUNCTIONAL DESCRIPTION Regeneration of the bit clock is achieved with an internal fully digital PLL. No external components are required and Demodulator the bit clock is not output. The PLL has two microcontroller control registers (addresses 1000 and 1001) for FRAME SYNC PROTECTION bandwidth and equalization. This circuit will detect the frame synchronization signals. For certain applications
ページ7に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc OTHER SUBCODE CHANNELS Write operation sequence Data of the other subcode channels (Q-to-W) may be read • RAB is held LOW by the microcontroller to hold the via the V4 pin if the versatile pins interface register SAA7345 DA pin at high-impedance. (address 1101) is set to XX01. • Microcontroller data is clocked into the internal shift register on the LOW-to-HIGH clock transition CL. The format i
ページ8に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc WRITING DATA TO SAA7345; REPEAT MODE The same command can be repeated several times (e.g. for fade function) by applying extra RAB pulses as shown in Fig.6. RAB (microcontroller) CL (microcontroller) DA A3 A2 A1 A0 D3 D2 D1 D0 (microcontroller) DA (SAA7345) high impedance MGA380 - 1 Note that CL must stay HIGH between RAB pulses. Fig.6 Microcontroller WRITE timing; repeat mode. READING
ページ9に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc RAB (microcontroller) CL (microcontroller) DA (microcontroller) high impedance DA (SAA7345) STATUS MGA381 - 1 Fig.7 SAA7345 status READ timing. READING Q-CHANNEL SUBCODE FROM SAA7345 To read Q-channel subcode from SAA7345, the SUBQREADY-I signal should be selected as status signal. The subcode read timing is shown in Fig.8. Read subcode operation sequence • Monitor SUBQREADY-I status si
ページ10に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc BEHAVIOUR OF THE SUBQREADY-I SIGNAL SHARING THE MICROCONTROLLER INTERFACE When the CRC of the Q-channel word is good, and no When the RAB pin is held LOW by the microcontroller, it is subcode is being read, the SUBQREADY-I signal will react permitted to put any signal on the DA and CL lines as shown in Fig.9. (SAA7345 will set output DA to high-impedance). Under this circumstance these lines ma
ページ11に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc TDA1301 SAA7345 I/O O MICROCONTROLLER O O MGA361 - 1 Fig.11 SAA7345 microcontroller interface application diagram. Table 2 Command registers. The ‘INITIAL’ column shows the power-on reset state REGISTER ADDRESS DATA FUNCTION INITIAL Fade and Attenuation 0 0 0 0 X 0 0 0 Mute Reset X 0 1 X Attenuate X 0 0 1 Full Scale X 1 0 0 Step Down X 1 0 1 Step Up Motor mode 0 0 0 1 X 0 0 0 Motor off mode Re
ページ12に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc REGISTER ADDRESS DATA FUNCTION INITIAL 2 DAC output 0 0 1 1 1 0 1 0 I S CD-ROM mode 1 0 1 1 EIAJ; CD-ROM mode 2 110 X I S; 4f mode Reset s 2 1111 I S; 2f mode s 2 1110 I S; f mode s 0 0 0 X EIAJ; 16-bit; 4f s 0 0 1 1 EIAJ; 16-bit; 2f s 0 0 1 0 EIAJ; 16-bit; f s 0 1 0 X EIAJ; 18-bit; 4f s 0 1 1 1 EIAJ; 18-bit; 2f s 0 1 1 0 EIAJ; 18-bit; f s Motor gain 0 1 0 0 X 0 0 0 Motor gain G = 3.2 Reset X 0
ページ13に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc REGISTER ADDRESS DATA FUNCTION INITIAL Loop BW Internal BW Low-pass (Hz) (Hz) BW (Hz) PLL loop filter bandwidth 1 0 0 0 0 0 0 0 1640 525 8400 0 0 0 1 3279 263 16800 0 0 1 0 6560 131 33600 0 1 0 0 1640 1050 8400 0 1 0 1 3279 525 16800 0 1 1 0 6560 263 33600 1 0 0 0 1640 2101 8400 1 0 0 1 3279 1050 16800 Reset 1 0 1 0 6560 525 33600 1 1 0 0 1640 4200 8400 1 1 0 1 3279 2101 16800 1 1 1 0 6560 1050
ページ14に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc REGISTER ADDRESS DATA FUNCTION INITIAL Versatile pins interface 1 1 0 1 0 0 0 0 4-line motor (using V4, V5) X X 0 1 Q-to-W subcode at V4 X X 1 0 V4 = 0 X X 1 1 V4 = 1 Reset 0 1 X X de-emphasis signal at V5 10 X X V5=0 1 1 X X V5 = 1 Reset Note 1. Standby modes = CL, DA and RAB; normal operation. a) MISC, SCLK, WCLK, DATA, CL11 and DOBM; 3-state. b) CRIN, CROUT, CL16 and CLA; normal operation. c
ページ15に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc Table 3 Digital filter passband characteristics PASSBAND ATTENUATION 0 to 19 kHz ≤ 0.001 dB 19 to 20 kHz ≤ 0.03 dB Table 4 Digital filter stopband characteristics. STOPBAND ATTENUATION 24 kHz ≥ 25 dB 24 to 27 kHz ≥ 38 dB 27 to 35 kHz ≥ 40 dB 35 to 64 kHz ≥ 50 dB 64 to 68 kHz ≥ 31 dB 68 kHz ≥ 35 dB 69 to 88 kHz ≥ 40 dB MGA385 20 magnitude (dB) 0 20 40 60 010 20 30 40 50 frequency (kHz) Fig.12 D
ページ16に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc Interpolation Hold Interpolation OK Error OK Error Error Error OK OK MGA372 Fig.13 Concealment mechanism. MUTE,ATTENUATION AND FADE To control the fade counter in a continuous way, the step-up and step-down commands are available (fade A digital level controller is present on the SAA7345 which control register data X101 and X100). They will increment performs the functions of soft mute, attenu
ページ17に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc Table 5 DAC interface formats DAC CONTROL SAMPLE MODE BITS SCLK (MHz) FORMAT INTERPOLATION REGISTER DATA FREQUENCY (1) 2 1 1010 f 16 2.1168 × n CD-ROM (I S) no s (1) (2) 2 1011 f 16 2.1168 × n CD-ROM (EIAJ) no s (1) 2 3 1110 f 16 2.1168 × n Philips I S - 16 bits yes s (1) 4 0010 f 16 2.1168 × n EIAJ - 16 bits yes s (1) 5 0110 f 18 2.1168 × n EIAJ - 18 bits yes s (1) 6000X 4f 16 8.4672 × n EIAJ
ページ18に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc 1998 Feb 16 18 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf
ページ19に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc EBU interface The biphase-mark digital output signal at pin DOBM is in accordance with the format defined by the “IEC 958” specification. Three different modes can be selected via the EBU output control register (address 1010). Table 6 EBU output modes EBU CONTROL EBU OUTPUT AT DOBM PIN EBU VALIDITY FLAG (BIT 28) REGISTER DATA XX11 DOBM pin held LOW - XX00 data taken before concealment, mute an
ページ20に含まれる内容の要旨
Philips Semiconductors Product specification CMOS digital decoding IC with RAM for SAA7345 Compact Disc CHANNEL STATUS The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192 channel status bits. The category code is always CD. The bit assignment is shown in Table 8. Table 8 EBU channel status WORD BITS FUNCTION Control 0 to 3 copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when copy permitted; bit 3 is logic 1 when recording ha
