ページ1に含まれる内容の要旨
ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU MANUAL
ARM720T Revision 4
(AMBA AHB Bus Interface Version)
CORE CPU MANUAL
ARM720T Revision 4
(AMBA AHB Bus Interface Version)
CORE CPU MANUAL
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
http://www.epsondevice.com
Document code: 405003400
Issue April, 2004
C
Printed in Japan A
ページ2に含まれる内容の要旨
NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permis- sion of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is appli- cable to products requirin
ページ3に含まれる内容の要旨
Preface 1 Introduction 2 Programmer’s Model 3 Configuration 4 Instruction and Data Cache 5Write Buffer 6 The Bus Interface 7 Memory Management Unit 8 Coprocessor Interface 9 Debugging Your System 10 ETM Interface 11 Test Support A Signal Descriptions Glossary Index
ページ4に含まれる内容の要旨
ページ5に含まれる内容の要旨
CONTENTS Contents Preface About this document................................................................................................xi 1 Introduction 1.1 About the ARM720T processor ................................................................. 1-1 1.2 Coprocessors ............................................................................................ 1-5 1.3 About the instruction set ............................................................................ 1-5 1.4 Silicon re
ページ6に含まれる内容の要旨
CONTENTS 6.9 Reset .......................................................................................................6-13 7 Memory Management Unit 7.1 About the MMU..........................................................................................7-1 7.2 MMU program-accessible registers ...........................................................7-3 7.3 Address translation....................................................................................7-4 7.4 MMU faults and CPU abo
ページ7に含まれる内容の要旨
CONTENTS 10 ETM Interface 10.1 About the ETM interface.......................................................................... 10-1 10.2 Enabling and disabling the ETM7 interface ............................................. 10-1 10.3 Connections between the ETM7 macrocell and the ARM720T processor................................................................................ 10-2 10.4 Clocks and resets .................................................................................... 10-3
ページ8に含まれる内容の要旨
CONTENTS List of Figures Figure 1-1 720T Block diagram ....................................................................................1-2 Figure 1-2 ARM720T processor functional signals.......................................................1-3 Figure 1-3 ARM instruction set formats ........................................................................1-7 Figure 1-4 Thumb instruction set formats...................................................................1-14 Figure 2-1 Big-endian ad
ページ9に含まれる内容の要旨
CONTENTS Figure 9-4 Clock synchronization ................................................................................. 9-8 Figure 9-5 The ARM720T core, TAP controller, and EmbeddedICE-RT macrocell ... 9-10 Figure 9-6 Domain Access Control Register .............................................................. 9-14 Figure 9-7 ARM720T processor scan chain arrangements........................................ 9-17 Figure 9-8 Test access port controller state transitions.........................
ページ10に含まれる内容の要旨
CONTENTS List of Tables Table 1-1 Key to tables ...............................................................................................1-6 Table 1-2 ARM instruction summary ...........................................................................1-8 Table 1-3 Addressing mode 2 ...................................................................................1-10 Table 1-4 Addressing mode 2 (privileged) ................................................................1-11 Table 1-5 Addr
ページ11に含まれる内容の要旨
CONTENTS Table 9-7 Determining the cause of entry to debug state ......................................... 9-32 Table 9-8 SIZE[1:0] signal encoding ......................................................................... 9-35 Table 9-9 Debug control register bit assignments..................................................... 9-39 Table 9-10 Interrupt signal control............................................................................... 9-40 Table 9-11 Debug status register bit assignmen
ページ12に含まれる内容の要旨
CONTENTS THIS PAGE IS BLANK. viii EPSON ARM DDI 0229B
ページ13に含まれる内容の要旨
Preface
ページ14に含まれる内容の要旨
ページ15に含まれる内容の要旨
Preface Preface This preface introduces the ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU Manual. It contains the following sections: About this document ................................................................................................. xi About this document This document is a technical reference manual for the ARM720T r4p2 processor. Intended audience This document has been written for experienced hardware and software engineers who might or might not have exper
ページ16に含まれる内容の要旨
Preface Chapter 8 Coprocessor Interface Read this chapter for a description on how to connect coprocessors to the ARM1156F-S coprocessor interface. Chapter 9 Debugging Your System Read this chapter for a description of the hardware extensions and integrated on-chip debug support for the ARM720T processor. Chapter 10 ETM Interface Read this chapter for a description of the Embedded Trace Macrocell support for the ARM720T processor. Chapter 11 Test Support Read this chapter for a descriptio
ページ17に含まれる内容の要旨
Preface Timing diagram conventions This manual contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labeled when they occur. Therefore, no additional meaning must be attached unless specifically stated. Clock HIGH to LOW Transient HIGH/LOW to HIGH Bus stable Bus to high impedance Bus change High impedance to stable bus Key to timing diagram conventions Shaded bus and signal areas are undefined, so the bus or signal c
ページ18に含まれる内容の要旨
Preface THIS PAGE IS BLANK. xiv EPSON ARM720T CORE CPU MANUAL
ページ19に含まれる内容の要旨
1 Introduction
ページ20に含まれる内容の要旨
