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Application Note: Spartan-II
MP3 NG: A Next Generation Consumer
R
Platform
XAPP169 (v1.0) November 24, 1999 Application Note
Summary This application note illustrates the use of Xilinx Spartan-II FPGA and an IDT RC32364 RISC
controller in a handheld, consumer electronics platform. Specifically the target application is an
MP3 audio player with advanced user interface features.
In this application the Spartan device is used to implement the complex system level glue logic
required to inte
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R MP3 NG: A Next Generation Consumer Platform MP3 Technology MP3 refers to the MPEG Layer 3 audio compression scheme that was defined as part of the International Standards Organization (ISO) Moving Picture Experts Group (MPEG) audio/video coding standard. MPEG-I defined three encoding schemes, referred to as Layer 1, Layer 2, and Layer 3. Each of these schemes uses increasing sophisticated encoding techniques and gives correspondingly better audio quality at a given bit rate. The three laye
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R MP3 NG: A Next Generation Consumer Platform 7 Serial Data SED1743 128 LCD Column Driver USBN9602 3 USB 128 x 128 Control Interface LCD Panel SED1758 2 Serial Data 128 & LCD Row 4 Wire Touch Driver 8 Membrane IRQ RC32364 Xilinx 32 Addr/Data 3 Serial Data MAX1108 RISC Spartan II 2 Channel CPU 21 Control FPGA ADC 2 Control Port L CS4343 To Stereo Audio Headphone 3 Serial Audio R IRMS6100 Jack DAC 3 IRDA Transceiver 16 Data 11 Address CompactFlash Interface 17 Control 11 Control 9 Control 8 MT48LC
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Enhanced JTAG (ICE Interface) R MP3 NG: A Next Generation Consumer Platform The variable page size lets each mapping independently represent memory regions that can range from 4 KB to 16 MB. This feature lets the system designer adjust the address mapping granularity for different memory regions. Locking TLB entries excludes entries from being recommended for replacement when there is an address miss. This lets the system designer have mappings for critical regions of code and or data locke
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R MP3 NG: A Next Generation Consumer Platform The RC32364 interfaces to the system through a 32-bit multiplexed address/data bus. The bus offers a rich set of signals to control transfers of which only a subset was required for this application. Figure 4 shows the timing for read transactions on this bus. MasterClock AD(31:0) Data Input Data Input Addr Addr Addr(3:2) Width(1:0) ALE Rd* Wr* CIP* DT/R* I/D* DataEn* Ack* Last* Figure 4: RC32364 Read Timing (Courtesy IDT) XAPP169 (v1.0) November
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R MP3 NG: A Next Generation Consumer Platform Crystal CS4343 The Digital-to-Analog Converter chosen for this design is the Crystal CS4343 from Cirrus Logic. This device features: Stereo DAC 1.8V to 3.3V operation. 24-bit conversion at up to 96 kHz. Digital volume control. Digital bass and treble boost. Built-in headphone amplifier capable of delivering 5 mW into a 16 Ω load. Figure 5 shows the block diagram for this device. The CS4343 provides three interfaces: the analog stereo head
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R MP3 NG: A Next Generation Consumer Platform RST t irs Repeated Stop Start Stop Start SDA t t t t t buf high hdst t f susp hdst SCL t t t t t sust sud r low hdd Figure 6: Control Port Timing (Courtesy Cirrus Logic) The serial port can be configured for several operating modes. The mode of operation chosen for this application is referred to in the CS4343 documentation as "Serial Audio Format 2". Figure 7 gives an overview of serial port timing when in this mode. Right Channel LRCK Left Chan
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R MP3 NG: A Next Generation Consumer Platform Samsung The FLASH memory chosen for this design is the KM29U64000T 8M x 8 device from Samsung Semiconductor. This device is based on NAND FLASH technology and is popular in MP3 player FLASH Memory applications due to its high density and low cost per bit. Figure 8 shows the block diagram for this device. The complete data sheet for the KM29U64000T can be found at the following URL: http://www.usa.samsungsemi.com/products/prodspec/flash/km29u64000
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R MP3 NG: A Next Generation Consumer Platform CLE tCEH CE tCHZ tWC WE tWB tAR2 tCRY ALE tRHZ tR tRC RE tRR A 0 ~ A 7 A9 ~ A 16 Dout N Dout N+1 Dout N+2 Dout N+3 Dout 527 00h or 01h A17 ~ A 22 I/O 0 - 7 Column Page(Row) t RB Address Address Busy R/ B Figure 9: KM29U64000T Read Timing (Courtesy Samsung Semiconductor) Micron SDRAM The SDRAM memory chosen for this design is the MT48LC1M16A1S - 512K x 16 x 2 bank device from Micron Semiconductor. This device is available in speed grades from 125 t
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R MP3 NG: A Next Generation Consumer Platform BANK0 ROW- MEMORY 11 ADDRESS 11 2,048 ARRAY LATCH (2,048 x 256 x 16) CKE CLK DQML, DQMH 256 (x16) CONTROL CS# LOGIC WE# CAS# SENSE AMPLIFIERS RAS# I/O GATING DQM MASK LOGIC DATA OUTPUT MODE REGISTER 256 16 REGISTER 12 DQ0- 16 COLUMN DQ15 8 8 DECODER 16 DATA INPUT 8 REGISTER 256 REFRESH ADDRESS CONTROLLER 12 SENSE AMPLIFIERS A0-A10, BA REGISTER I/O GATING DQM MASK LOGIC REFRESH 11 COUNTER ROW- ADDRESS 256 (x16) MUX 11 BANK1 ROW- MEMORY 11 ADDRESS 11
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R MP3 NG: A Next Generation Consumer Platform National The USB interface in the design is based on a National Semiconductor USBN9602 controller. This device, packaged in a 28-pin SOIC package, supports full speed USB function controller Semiconductor operation and includes an integrated USB transceiver. It contains seven endpoint FIFOs, two of USBN9602 USB which are 64 bytes deep. Function Figure 12 shows a block diagram of this device. The complete data sheet for the USBN9602 Controller
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R MP3 NG: A Next Generation Consumer Platform ALE CS RD or WR AD[7:0] ADDR DATA Figure 13: USBN9602 Read / Write Cycle Timing (Courtesy National Semiconductor) System This section describes how all of these pieces are integrated into a complete system. First described is the software architecture and the functionality of the key modules. Next is the Implementation architecture and implementation of the logic contained in the Spartan-II FPGA. Software Architecture The system software require
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R MP3 NG: A Next Generation Consumer Platform UI Manager RTOS MP3 Decoder Audio Memory ISR Manager IRDA USB Stack Stack IR USB Touch Screen Audio FLASH MMU BIOS BIOS BIOS BIOS BIOS BIOS BIOS System Hardware Figure 14: System Software Architecture The RTOS provides process scheduling and memory allocation functions. The RTOS could be any of the commercially available packages. Probably more of a factor than any technical issue is the licensing model for the product. Since this is a product th
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R MP3 NG: A Next Generation Consumer Platform The reference code that was developed for the standard is available from the Fraunhofer Institute at the following URL: http://www.iis.fhg.de/amm/techinf/layer3/index.html A commercial decoder is available from Xaudio. Information on the Xaudio product line is available from: http://www.xaudio.com Memory Manager The Memory Manager handles the tasks required to mask NAND FLASH issues from the other software in the system. Specifically these tasks a
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R MP3 NG: A Next Generation Consumer Platform LCD Controller D_IN[31:0] LCD Control A_OUT[31:2] Signals Control Out MUX DAC Interface D_OUT[31:0] D_IN[31:0] DAC Interface Signals A_IN[3:2] MUX Control In CPU Interface Touch Screen D_OUT[31:0] CPU Address/Data Interface D_IN[31:0] CPU Control A_OUT[31:2] D_OUT[31:0] USB Control D_IN[31:0] Control Out ADC Interface Signals A_IN[3:2] Control In IRDA Controller Memory Interface D_OUT[31:0] D_OUT[31:0] D_IN[31:0] D_IN[31:0] Memory Data Tranceiver Int
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R MP3 NG: A Next Generation Consumer Platform CPU Interface The CPU Interface block performs three functions: protocol conversion, CPU initialization and address de-multiplexing. Figure 16 shows a block diagram of this block. CPU Initialization CPU_COLDRESET_N IR_INT_N CPU_RESET_N DAC_INT_N CPU_BUSGNT_N CPU_INT_N[3:0] SYS_CLK DIN[31:0] CPU_AD[31:0] DOUT[31:0] Latch 28 28 AOUT[31:4] DQ CPU_ALE Enable 2 CPU_ADDR[3:2] AOUT[3:2] CPU_MASTERCLK Bus State Machine CPU_CIP_N SYS_CLK CPU_BE_N[3:0] CPU_RD
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R MP3 NG: A Next Generation Consumer Platform Table 1: CPU Interface Signal Summary Signal Type Description CPU_MASTERCLK Output All bus timing is relative to this clock. The CPU core frequency is derived by multiplying this clock. CPU_AD[31:0] I/O High-order multiplexed address and data bits. CPU_ADDR[3:2] Input Non-multiplexed address lines. These serve as the word within block address for cache refills (Addr[3:2]). CPU_BE_N[3:0] Input Indicates which byte lanes are expected to participat
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R MP3 NG: A Next Generation Consumer Platform Shift FIFO Register 32 32 4 DI_D[3:0] DIN[31:0] DQ DQ Enable Wr Rd Load State Machine SYS_CLK DI_XSCL BREQ_N DI_LP BGNT_N DI_FR RD_N DI_YD ACK_N DI_YSCL Address Counter 9 9 9 AOUT[10:2] Q D Enable Load 21 Base AOUT[31:11] Address Figure 17: LCD Controller Block Diagram The LCD Controller is an IP bus master and fetches data for screen refresh independently of CPU activities. The display data that is fetched is loaded into a FIFO using a block trans
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R MP3 NG: A Next Generation Consumer Platform The only software support required for this block is the screen BIOS which consists of functions to generate screen images by manipulating the frame buffer memory. This buffer appears as an array of 512, 32-bit words with each word containing 32 pixels of the screen image. The most significant bit of the word at the base address appears as the pixel in the upper left-hand corner nd of the screen. The least significant bit of that memory word appe
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R MP3 NG: A Next Generation Consumer Platform SDRAM Controller The SDRAM controller design (Figure 19) is based on the design developed by Xilinx in application note XAPP134: Virtex Synthesizable High Performance SDRAM Controller. The changes made in the original design are to adapt to the differences in the host interface. In the original design the host interface is a multiplexed address data bus. In this application the IP bus is non-multiplexed. Another difference is that the original de
