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CDCM7005 (QFN Package)
Evaluation Module Manual
HPA/High Speed Communications
User’s Guide
2005 Clock Drivers
SCAU015
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the t
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EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically found in the end product
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EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the supply voltage range of 3 V and 3.6 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult t
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Related Documentation From Texas Instruments Preface Read This First About This Manual This manual explains how to use the CDCM7005 evaluation module (EVM) and provides guidelines to build the customer’s own systems. The manual includes schematics, layout, bill of materials, and a software description. How to Use This Manual This document contains the following chapters: Chapter 1—Introduction Chapter 2—Quick Start Chapter 3—EVM Hardware Chapter 4—Serial Peripheral Interface (SPI) Softw
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 CDCM7005 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 2 Quick Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3 EVM Hardware . . . . . . . . . . . . . .
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Contents Figures 3 −1 Board View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 4 −1 Screen View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 5 −1 CDCM7005 With a Passive Loop Filter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5 −2 CDCM7005 With an External Active Loop Filter Using OPA341 . .
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Chapter 1 Introduction The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes an on-board voltage controlled crystal oscillator (VC(X)O) frequency to an external reference clock. The device operates up to 2.2 GHz. The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements by selecting the external VC(X)O, loop filter components, frequency for PFD, and charge pump current. Each of the five differential LVPECL an
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CDCM7005 Functional Block Diagram 1.1 CDCM7005 Functional Block Diagram AVCC VCC VCC_CP Selected REF Signal STATUS_REF / PRI_SEC_CLK Manual & STATUS_VCXO REF_SEL Automatic / I_REF_CP freq. detect CLK Select > 2 MHz PLL_LOCK freq. detect > 2 MHz LOCK HOLD PRI_REF Progr. Delay Progr. Divider LVCMOS 10 M M 2 Reference Clock SEC_REF Charge CP_OUT PFD Pump Feedback Progr. Delay Progr. Divider 12 Clock N N 2 Current SPI LOGIC CTRL_LE Reference CTRL_DATA CTRL_CLK PECL to LV LVCMOS CMOS Y0A PD LV PE
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Chapter 2 Quick Start In order to setup the EVM quickly and to take some measurements at default settings, the following actions are required: Supply 3.3 V to P1, LED D4 will be on. Apply a single-ended reference clock to the reference clock input PRI_REF (pin A1) or SEC_REF (pin B1). For default setting, the reference th clock must be 1/8 of the VC(X)O frequency. If REF_SEL is set to 1, then PRI_REF is selected. If REF_SEL is set to 0, then SEC_REF is selected. This selection can be reali
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Chapter 3 EVM Hardware This chapter discusses the EVM hardware. Topic Page 3.1 Board View and Connector Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 EVM Hardware 3-1
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Board View and Connector Location 3.1 Board View and Connector Location Figure 3 −1. Board View 3.2 Hardware Configuration This section describes the board configuration using on-board jumpers and solder bridges. 3.2.1 Power Supply (P1, P2) Supply 3.3 V ±10% on P1 and P2 using a stabilized external power supply. WARNING: Never supply more than 3.6 V on P1. 3.2.2 Onboard Switches and Indicators (SW1 −SW2, D1 −D4) Push SW1 to enter the power-down mode of the CDCM7005 device. Then all curren
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Hardware Configuration 3.2.3 Programming Interfaces (J30, J31) The SPI of the device is used for writing to the control register of the device. It consists of three control lines CTRL_CLK, CTRL_DATA, and CTRL_LE. There are four 30-bit wide RAM registers, which can be addressed by the two LSBs of a transferred word. Every transmitted word must have 32 bits, starting with MSB. After supplying power or activating the power-down mode, the registers are loaded with the device default values internall
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Hardware Configuration When the CDCM7005 is powered up, it defaults to five LVPECL outputs. However, this EVM is configured as follows: Y0 − Y2 = LVPECL Y3, Y4 = LVCMOS (in addition Y4 has an option for a custom filter) The reference input clock signal has to be applied to J1 or J6. The reference input clock signal can be sensed on J4. In this case, close the bridge J5 (the oscilloscope’s 50 Ω may be used to terminate the 50-Ω trace). The reference input clock sense line is matched to the LV
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Chapter 4 Serial Peripheral Interface (SPI) Software This chapter discusses the serial peripheral interface software. Topic Page 4.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Serial Peripheral Interface (SPI) Software 4-1
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Functional Description 4.1 Functional Description Programming software here as described is intended for programming the in- ternal control register of the CDCM7005. The software runs under Win- dows98, NT, 2000, and XP. A quick installation is required prior to use. See the Software Installation section. There are several cases where programming is mandatory. As a rule of thumb here are some examples: Use of active loop filter Change of divider ratio or disable of certain LVPECL/LVCMOS outp
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Chapter 5 Application Circuit Diagram This chapter discusses the application circuit diagram. Topic Page 5.1 Application Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Application Circuit Diagram 5-1
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Application Circuit Diagram 5.1 Application Circuit Diagram The following applications sections the two loop filter configurations are discussed. 5.1.1 Passive Loop Filter The passive loop filter is a second order filter (two poles, one zero). The zero is required for the overall loop stability. R1, C1, and C2 generate the dominant pole of the system. A second pole is introduced by R2 and C3. Figure 5 −1. CDCM7005 With a Passive Loop Filter Configuration Low-Pass Filter VC(X)O R2 491.52 MHz 160
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Application Circuit Diagram 5.1.2 External Active Loop Filter Using OPA341 Figure 5 −2. CDCM7005 With a External Active Loop Filter Using OPA341 Low-Pass Filter VC(X)O R3 491.52 MHz 10 kΩ PECL_OUT_B V_CTRL PECL_OUT C3 100 nF C2 R2 10 µF Vcc 4.7 kΩ Vcc CDCM7005 R5 PRI_REF 10 kΩ InN SEC_REF R1 OPA341 Out 180 Ω InP CP_OUT R6 C1 CTRL_LE STATUS_REF 10 kΩ 100 nF C1 SPI CTRL_DATA STATUS_VC(X)O 100 nF CTRL_CLK PLL_LOCK V V CC CC 130 Ω 10 nF YnA 130 Ω VC(X)O_IN 10 nF VC(X)O_IN YnB R R R 150 Ω 150
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Chapter 6 Parts List, Board Layout, and Schematics This chapter contains the parts list, board layout, and schematics for the CDCM7005 EVM. Topic Page 6.1 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.3 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
