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TMS320C67x/C67x+ DSP
CPU and Instruction Set
Reference Guide
Literature Number: SPRU733
May 2005
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the t
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Preface Read This First About This Manual The TMS320C6000™ digital signal processor (DSP) platform is part of the TMS320™ DSP family. The TMS320C62x™ DSP generation and the TMS320C64x™ DSP generation comprise fixed-point devices in the C6000™ DSP platform, and the TMS320C67x™ DSP generation comprises floating-point devices in the C6000 DSP platform. The TMS320C67x+™ DSP is an enhancement of the C67x™ DSP with added functionality and an expanded instruction set. This document describes the CPU ar
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Trademarks Related Documentation From Texas Instruments / Trademarks TMS320C672x DSP Peripherals Overview Reference Guide (literature number SPRU723) describes the peripherals available on the TMS320C672x DSPs. TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the TMS320C62x and TMS320C67x DSPs, development tools, and third-party support. TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and assembly code for the TMS320C6000 DS
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Summarizes the features of the TMS320 family of products and presents typical applications. Describes the TMS320C67x DSP and lists their key features. 1.1 TMS320 DSP Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 TMS320C6000 DSP Family Overview . . . . .
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Contents 3 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the assembly language instructions of the TMS320C67x DSP. Also described are parallel operations, conditional operations, resource constraints, and addressing modes. 3.1 Instruction Operation and Execution Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Instruction Syntax and Opcode Notat
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Contents CLR (Clear a Bit Field) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77 CMPEQ (Compare for Equality, Signed Integers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80 CMPEQDP (Compare for Equality, Double-Precision Floating-Point Values) . . . . . . . 3-82 CMPEQSP (Compare for Equality, Single-Precision Floating-Point Values) . . . . . . . . 3-84 CMPGT (Compare for Greater Than, Signed Integers) . . . . . . .
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Contents MPYI (Multiply 32-Bit by 32-Bit Into 32-Bit Result) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-157 MPYID (Multiply 32-Bit by 32-Bit Into 64-Bit Result) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-159 MPYLH (Multiply Signed 16 LSB by Signed 16 MSB) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-161 MPYLHU (Multiply Unsigned 16 LSB by Unsigned 16 MSB) . . . . . . . . . . . . . . . . . . . . 3-163 MPYLSHU (Multiply Signed 16 LSB by Unsigned 16 MSB) . . .
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Contents SPINT (Convert Single-Precision Floating-Point Value to Integer) . . . . . . . . . . . . . . . 3-228 SPTRUNC (Convert Single-Precision Floating-Point Value to Integer With Truncation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-230 SSHL (Shift Left With Saturation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-232 SSUB (Subtract Two Signed Integers With Saturation) . . . . . . . . . . . . . . . . . .
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Contents 4.2.11 MPYI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 4.2.12 MPYID Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4.2.13 MPYDP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 4.2.14 MPYSPDP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents A Instruction Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Lists the instructions that are common to the C62x, C64x, and C67x DSPs. B Mapping Between Instruction and Functional Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Lists the instructions that execute on each functional unit. C .D Unit Instructions and Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figures Figures 1 −1 TMS320C67x DSP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 2 −1 TMS320C67x CPU Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2 −2 Storage Scheme for 40-Bit Data in a Register Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2 −3 Addressing Mode Register (AMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figures 4 −18 Two-Cycle DP Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 4 −19 Four-Cycle Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 4 −20 INTDP Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 4 −21 DP Compare Instruction Phases . . . . . . . . . . . . . . . . . . . .
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Tables Tables 1 −1 Typical Applications for the TMS320 DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2 −1 40-Bit/64-Bit Register Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2 −2 Functional Units and Operations Performed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2 −3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Tables 3 −19 Data Types Supported by LDH(U) Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-131 3 −20 Data Types Supported by LDH(U) Instruction (15-Bit Offset) . . . . . . . . . . . . . . . . . . . . . . 3-135 3 −21 Register Addresses for Accessing the Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . 3-182 4 −1 Operations Occurring During Pipeline Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4 −2 Execut
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Tables 5 −1 Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5 −2 Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 A−1 Instruction Compatibility Between C62x, C64x, C67x, and C67x+ DSPs . . . . . . . . . . . . . . A-1 B−1 Functional Unit to Instruction Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Examples Examples 3 −1 Fully Serial p-Bit Pattern in a Fetch Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3 −2 Fully Parallel p-Bit Pattern in a Fetch Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3 −3 Partially Serial p-Bit Pattern in a Fetch Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3 −4 LDW Instruction in Circular Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1 a Introduction The TMS320C6000™ digital signal processor (DSP) platform is part of the TMS320™ DSP family. The TMS320C62x™ DSP generation and the TMS320C64x™ DSP generation comprise fixed-point devices in the C6000™ DSP platform, and the TMS320C67x™ DSP generation comprises floating- point devices in the C6000 DSP platform. All three DSP generations use the VelociTI™ architecture, a high-performance, advanced very long instruction word (VLIW) architecture, making these DSPs excellent c
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TMS320 DSP Family Overview TMS320 DSP Family Overview / TMS320C6000 DSP Family Overview 1.1 TMS320 DSP Family Overview The TMS320™ DSP family consists of fixed-point, floating-point, and multipro- cessor digital signal processors (DSPs). TMS320™ DSPs have an architec- ture designed specifically for real-time signal processing. Table 1 −1 lists some typical applications for the TMS320™ family of DSPs. The TMS320™ DSPs offer adaptable approaches to traditional signal-processing problems. They also
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TMS320C6000 DSP Family Overview Table 1 −1. Typical Applications for the TMS320 DSPs Automotive Consumer Control Adaptive ride control Digital radios/TVs Disk drive control Antiskid brakes Educational toys Engine control Cellular telephones Music synthesizers Laser printer control Digital radios Pagers Motor control Engine control Power tools Robotics control Global positioning Radar detectors Servo control Navigation Solid-state answering machines Vibration analysis Voice commands General-Purpo
