Summary of the content on the page No. 1
TMS3320C5515 DSP System
User's Guide
Literature Number: SPRUFX5A
October 2010–Revised November 2010
Summary of the content on the page No. 2
2 SPRUFX5A–October 2010–Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Summary of the content on the page No. 3
Contents Preface ....................................................................................................................................... 9 1 System Control ................................................................................................................. 13 1.1 Introduction ................................................................................................................. 13 1.1.1 Block Diagram .........................................................
Summary of the content on the page No. 4
www.ti.com List of Figures 1-1. Functional Block Diagram ................................................................................................ 13 1-2. DSP Memory Map ........................................................................................................ 17 1-3. DSP Clocking Diagram .................................................................................................. 22 1-4. Clock Generator ..................................................................
Summary of the content on the page No. 5
www.ti.com 1-48. EMIF System Control Register (ESCR) [1C33h]...................................................................... 76 1-49. EMIF Clock Divider Register (ECDR) [1C26h] ........................................................................ 77 5 SPRUFX5A–October 2010–Revised November 2010 List of Figures Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Summary of the content on the page No. 6
www.ti.com List of Tables 1-1. ............................................................................................................................... 14 1-2. DARAM Blocks ............................................................................................................ 17 1-3. SARAM Blocks............................................................................................................. 18 1-4. SAROM Blocks ............................................................
Summary of the content on the page No. 7
www.ti.com 1-48. Output Slew Rate Control Register (OSRCR) Field Descriptions................................................... 66 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions ...................................................... 67 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions ...................................................... 68 1-51. Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions ......................................................
Summary of the content on the page No. 8
8 List of Tables SPRUFX5A–October 2010–Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Summary of the content on the page No. 9
Preface SPRUFX5A–October 2010–Revised November 2010 Read This First About This Manual This document describes various aspects of the TMS320C5515 digital signal processor (DSP) including: system memory, device clocking options and operation of the DSP clock generator, power management features, interrupts, and system control. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (
Summary of the content on the page No. 10
Related Documentation From Texas Instruments www.ti.com SPRUFO4 — TMS320C5515/14/05/04/VC05/VC04 Digital Signal Processor (DSP) General-Purpose Input/Output (GPIO) User's Guide. This document describes the general-purpose input/output (GPIO) on the TMS320C5515/14/05/04/VC05/VC04 digital signal processor (DSP) devices. The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an input, you can detect the state of an internal
Summary of the content on the page No. 11
www.ti.com Related Documentation From Texas Instruments SPRUGH5— TMS320C5505 DSP System User's Guide. This document describes various aspects of the TMS320C5505 digital signal processor (DSP) including: system memory, device clocking options and operation of the DSP clock generator, power management features, interrupts, and system control. SPRUFX6— TMS320C5514 DSP System User's Guide. This document describes various aspects of the TMS320C5514 digital signal processor (DSP) including: system mem
Summary of the content on the page No. 12
12 Read This First SPRUFX5A–October 2010–Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Summary of the content on the page No. 13
Chapter 1 SPRUFX5A–October 2010–Revised November 2010 System Control 1.1 Introduction The TMS320C5515 digital signal processor (DSP) contains a high-performance, low-power DSP to efficiently handle tasks required by portable audio, wireless audio devices, industrial controls, software defined radio, fingerprint biometrics, and medical applications. The C5515 DSP consists of the following primary components: • A C55x CPU and associated memory • FFT hardware accelerator • Four DMA controllers and
Summary of the content on the page No. 14
Introduction www.ti.com 1.1.2 CPU Core The C55x CPU is responsible for performing the digital signal processing tasks required by the application. In addition, the CPU acts as the overall system controller, responsible for handling many system functions such as system-level initialization, configuration, user interface, user command execution, connectivity functions, and overall system control. Tightly coupled to the CPU are the following components: • DSP internal memories – Dual-access RAM (DA
Summary of the content on the page No. 15
www.ti.com Introduction Note that for the FFT routines, output data is dependent on the return value (T0). If return = 0 output data is in-place, meaning the result will overwrite the input buffer. If return =1, output data is placed in the scratch buffer. The 32-bit input and output data consist of 16-bit real and 16-bit imaginary data. If only real data is used, the imaginary part can be zeroed. The Scale flag determines if the butterfly output is divided by 2 to prevent overflow at the expens
Summary of the content on the page No. 16
System Memory www.ti.com modes. • Three 32-bit timers with 16-bit prescaler; one timer supports watchdog functionality. • A USB 2.0 slave. • A 10-bit successive approximation (SAR) analog-to-digital converter with touchscreen conversion capability. • One real-time clock (RTC) with associated low power mode. 1.2 System Memory The DSP supports a unified memory map (program code sections and data sections can be mixed and interleaved within the entire memory space) composed of both on-chip and exte
Summary of the content on the page No. 17
www.ti.com System Memory Figure 1-2. DSP Memory Map CPU BYTE DMA/USB/LCD (A) (A) ADDRESS BYTE ADDRESS MEMORY BLOCKS BLOCK SIZE 000000h 0001 0000h (B) MMR (Reserved) 0000C0h 0001 00C0h (D) 64K Minus 192 Bytes DARAM 010000h 0009 0000h SARAM 256K Bytes 050000h 0100 0000h (C)(E) 8M Minus 320K Bytes SDRAM/mSDRAM External-CS0 Space 800000h 0200 0000h (C) External-CS2 Space 4M Bytes Asynchronous C00000h 0300 0000h (C) External-CS3 Space 2M Bytes Asynchronous E00000h 0400 0000h (C) 1M Bytes Asynchronous
Summary of the content on the page No. 18
System Memory www.ti.com Table 1-2. DARAM Blocks (continued) Memory Block CPU Byte Address Range DMA/USB Controller Byte Address Range DARAM 6 00 C000h - 00 DFFFh 0001 C000h - 0001 DFFFh DARAM 7 00 E000h - 00 FFFFh 0001 E000h - 0001 FFFFh 1.2.1.2 On-Chip Single-Access RAM (SARAM) The SARAM is located at the CPU byte address range 01 0000h - 04FFFFh and is composed of 32 blocks of 4K words each (see Table 1-3). Each SARAM block can perform one access per cycle (one read or one write). SARAM can b
Summary of the content on the page No. 19
www.ti.com System Memory 1.2.1.3 On-Chip Single-Access Read-Only Memory (SAROM) The zero-wait-state ROM is located at the CPU byte address range FE 0000h - FF FFFFh. The ROM is composed of four 16K-word blocks, for a total of 128K-bytes of ROM. Each ROM block can perform one access per cycle (one read or one write). ROM can be accessed by the internal program or data buses, but not the DMA buses. The ROM address space can be mapped by software to the external memory or to the internal ROM via th
Summary of the content on the page No. 20
Device Clocking www.ti.com pins for the load mode register command. During the mobile SDRAM initialization, the device issues the load mode register initialization command to two different addresses that differ in only the BA0 and BA1 address bits. These registers are the Extended Mode register and the Mode register. The extended mode register exists only in mSDRAM, and not in non-mSDRAM. If a non-mobile SDRAM memory ignores bits BA0 and BA1, the second loaded register value overwrites the first
