Summary of the content on the page No. 1
FuturePlus® Systems
Corporation
DDR2 DIMM HIGH SPEED PROBE
FS2334
Users Manual
For use with Agilent Technologies Logic Analyzers
Revision 1.1
FuturePlus is a trademark of FuturePlus Systems Corporation
Copyright 2006 FuturePlus Systems Corporation
Summary of the content on the page No. 2
How to reach us.......................................................................................................................4 Product Warranty....................................................................................................................5 Limitation of warranty................................................................................................................... 5 Exclusive Remedies ..................................................................
Summary of the content on the page No. 3
Overview........................................................................................................................................ 18 State Analysis Operation – Read and Writes above 667MT/s....................................................................18 State Analysis Operation – Read and Write at 667MT/s or slower ............................................................19 State Analysis Operation – Read or Write at 800MT/s ............................................
Summary of the content on the page No. 4
How to reach us For Technical Support: FuturePlus Systems Corporation 36 Olde English Road Bedford NH 03110 TEL: 603-471-2734 FAX: 603-471-2738 On the web http://www.futureplus.com For Sales and Marketing Support: FuturePlus Systems Corporation TEL: 719-278-3540 FAX: 719-278-9586 On the web http://www.futureplus.com FuturePlus Systems has technical sales representatives in several major countries. For an up to date listing please see http://www.futureplus.com/contac
Summary of the content on the page No. 5
Product Warranty Due to wide variety of possible customer target implementations, the FS2334 DDR2 DIMM probe has a 30 day acceptance period by the customer from the date of receipt. If the customer does not contact FuturePlus Systems within 30 days of the receipt of the product it will be said that the customer has accepted the product. If the customer is not satisfied with the FS2334 DDR2 DIMM probe they may return the FS2334 within 30 days for a refund. This FuturePlus Systems® prod
Summary of the content on the page No. 6
Software License Agreement IMPORTANT - Please read this license agreement carefully before opening the media envelope. Rights in the software are offered only on the condition that the customer agrees to all terms and conditions of the license agreement. Opening the media envelope indicates your acceptance of these terms and conditions. If you do not agree to the licensing agreement, you may return the unopened package for a full refund. License Agreement In return for payment for t
Summary of the content on the page No. 7
Introduction Thank you for purchasing the FuturePlus Systems FS2334 DDR2 DIMM Interposer Logic Analyzer Probe. We think you will find the FS2334, along with your Agilent Technologies Logic Analyzer, a valuable tool for helping to characterize and debug your DDR2-based systems. This Users Guide will provide the information you need to install, configure, and use the DDR2 Probe. If you have any questions about this Guide or use of this probe, please contact FuturePlus Systems Corporation
Summary of the content on the page No. 8
FS2334 Probe Description The FS2334 DDR2 Probe allows you to perform timing analysis measurements on DDR2 DIMM busses. It also provides a Protocol Decoder with the capability of providing State analysis of both Read and Write activity is provided by using the dual sample mode feature available on the 169xx. The interposer design of this probe allows any DDR2 connection to be probed while it supports a DDR2 DIMM module. Probe Technical Feature Summary • Quick and easy connection betwee
Summary of the content on the page No. 9
Signal Assignments on Probe Pods The overlap in the bit ranges (for DQxx) signals between pods occurs because the bits are assigned to pods in the order that they appear physically on the DDR2 DIMM connector, which is not strictly in logical bit order. This allows the Probe layout to better match stub lengths among all DQxx signals. See the Appendix for a detailed list of how Logic Analyzer Channels are mapped to signals and DDR2 pins. Signal Threshold Voltage Settings The standard v
Summary of the content on the page No. 10
FS2334 Frontside layout Header 3 Header 4 Header 5 Header 1 Header 7 Header 8 Header 6 1.25” Header 14 FS2334 Backside layout TP 5 Header 2 Header 13 Header 11 Header 10 Header 12 TP 1,2,3,7 Header 9 TP 6 TP 4 Test Points There are several test point on the board. The first set of test points are used to select which signals go to the Clk input and the D15 input of Header 2. The shipping configuration for the FS2334 is to have S0 wired to the Clk input, which is TP3 wired to TP2.
Summary of the content on the page No. 11
Connecting to your Target System To connect the probe to the DDR2 bus, select an available DDR2 slot. Remove the DDR2 DIMM module, if present. Install the DDR2 DIMM module into the 240 pin connector on the top of the FS2334 probe. Install the DDR2 probe/DIMM into the target system. Connect the supplemental power supply to the FS2334. Connect the FS2334 Headers directly to the logic analyzer pods per the configuration file requirements if not done prior to installing the probe. Refer to
Summary of the content on the page No. 12
Recommended Logic Analyzer Card Requirements and Configuration files 169xx Analyzer Timing Analysis State Analysis Type 667MT/s or slower 16753/4/5/6, FS234_2 3 cards FS234_5 4 cards configured as one configured as one logic 16950 module, one timing analyzer state machine. machine Uses FS1117 800MT/s 16753/4/5/6, FS234_2 3 cards FS234_1 Read and Write configured as one analysis requires 7 cards 16950 module, one timing across 2 frames machine configured as 2 logic analyz
Summary of the content on the page No. 13
Logic Analyzer card configurations – Note: These are all for unbuffered DIMM probing FS234_1 2 machine, 7 Card 800MT/s Write – Command machine 4 cards in slots A – D (B = Read and Write configuration file Master). Read machine 3 cards in slots A – C (B = master) FS234_32_Lower(Upper) 4 card 32 bit 4 cards in slots A – D (B = Master) 800MT/s Data State analysis configuration FS234_2 Timing analysis 3 card 3 cards in slots A – C (B = Master) configuration FS234_3 800MT/s Writes onl
Summary of the content on the page No. 14
Software Requirements Setting up the 169xx Analyzer A CD containing the 16900 software is included in the FS1136 package. The CD contains a setup file that will automatically install the configuration files and protocol decoder onto a PC containing the 16900 operating system or onto a 16900 analyzer itself. To install the software simply double click the .exe file on the CD containing the FS1136 and the FS1117 software. After accepting the license agreement the software should instal
Summary of the content on the page No. 15
Offline Analysis Offline analysis allows a user to be able to analyze a trace offline at a PC so it frees up the analyzer for another person to use the analyzer to capture data. If you have already used the license that was included with your package on a 1680/90/900 analyzer and would like to have the offline analysis feature on a PC you may buy additional licenses, please contact FuturePlus sales department. In order to view decoded data offline, after installing the 1680/90/900
Summary of the content on the page No. 16
After the decoder has loaded, select Preferences from the overview screen and set the preferences to their correct value in order to decode the trace properly. The protocol decoders, FS1136 and FS1117, require 4 parameters to be entered by the user in order to decode valid states. To access the preferences on the 169xx select Prefs from the graphic representation of the protocol decoder in the overview window. The information required is generally available from the spec. sheet of the me
Summary of the content on the page No. 17
TimingZoom Analysis The TimingZoom feature of the 1690x logic analyzer allows for efficient timing analysis of all the signals on the DDR2 DIMM bus. Please refer to the “Setting up the 16900 Analyzer” section of this manual on the use of the general purpose probe feature to determine how to attach the logic analyzer to the probe. Load the logic analyzer configuration file for timing, FS234_2. It doesn't matter whether you select to load "Configs only" or "Configs and Data". You are now
Summary of the content on the page No. 18
State Analysis Overview There are several choices for State mode analysis using the FS2334 DDR2 probe depending on the speed of the data bus being probed and the number of logic analyzer cards available to the user. At data speeds of up to 667MT/s the logic analyzer can be triggered on BOTH edges of the clock signal used for State analysis (state clock), at a data speed of 800MT/s ONLY the rising edge of the state clock can be used. Because the sampling point for a data signal is at a
Summary of the content on the page No. 19
State Analysis Operation – Read and Write at 667MT/s or slower State mode capture is performed by using both edges of CK0. This double probing of each signal is handled internally by the Agilent Logic Analyzer using the Dual Sample mode feature. State analysis within these parameters only requires dual sampling of the Data signals, which can be done with 4 cards in one frame. The four cards used for state analysis must be configured as one logic analyzer machine. You may also place t
Summary of the content on the page No. 20
The process for setting sampling positions at speeds of 800MT/s: This procedure requires the probe user to capture TimingZoom traces and use the markers to determine the correct sampling positions. This is an iterative, trial and error procedure where adjustments to Data signal sampling positions may need to be adjusted several times before they provide correct State data capture on both Read and Writes. When operating at 800MT/s data speed and a Multi-Frame configuration. There are s
