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CY7C1292DV18
CY7C1294DV18
9-Mbit QDR- II™ SRAM 2-Word
Burst Architecture
Features Functional Description
• Separate Independent Read and Write data ports The CY7C1292DV18 and CY7C1294DV18 are 1.8V
Synchronous Pipelined SRAMs, equipped with QDR™-II
— Supports concurrent transactions
architecture. QDR-II architecture consists of two separate
• 250-MHz clock for high bandwidth
ports to access the memory array. The Read port has
• 2-Word Burst on all accesses
dedicated Data Outputs to support Read
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128K x 36 Array 256K x 18 Array 128K x 36 Array 256K x 18 Array CY7C1292DV18 CY7C1294DV18 Logic Block Diagram (CY7C1292DV18) D [17:0] 18 Write Write Address A Reg (17:0) Reg Register 18 Address Register A (17:0) 18 RPS K Control CLK K Logic Gen. C DOFF Read Data Reg. CQ C CQ 36 18 V REF 18 Reg. Reg. 18 WPS Control Logic 18 BWS [1:0] Reg. Q [17:0] 18 Logic Block Diagram (CY7C1294DV18) D [35:0] 36 Write Write Address A Reg Reg (16:0) Address Register 17 Register A (16:0) 17 RPS K Control CLK K Lo
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CY7C1292DV18 CY7C1294DV18 Pin Configurations 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1292DV18 (512K x 18) 1 23 4 5 6 7 89 10 11 A CQ NC/144M NC/36M WPS BWS K NC/288M RPS NC/18M NC/72M CQ 1 B NC Q9 D9 A NC K BWS A NC NC Q8 0 NC NC D10 V AAA V NC Q7 D8 C SS SS D NC D11 Q10 V V V V V NC NC D7 SS SS SS SS SS E NC NC Q11 V V V V V NC D6 Q6 DDQ SS SS SS DDQ NC Q12 D12 V V V V V NC NC Q5 F DDQ DD SS DD DDQ NC D13 Q13 V V V V V NC NC D5 G DDQ DD SS DD DDQ V V V V V V V V V ZQ H DOFF REF DDQ DDQ
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CY7C1292DV18 CY7C1294DV18 Pin Definitions Pin Name I/O Pin Description D Input- Data input signals, sampled on the rising edge of K and K clocks during valid write [x:0] Synchronous operations. CY7C1292DV18 - D [17:0] CY7C1294DV18 - D [35:0] WPS Input- Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted Synchronous active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D to be ignored. [x:0
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CY7C1292DV18 CY7C1294DV18 Pin Definitions (continued) Pin Name I/O Pin Description DOFF Input DLL Turn Off, active LOW. Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. TDO Output TDO for JTAG. TCK Input TCK pin for JTAG. TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. NC N/A Not connected to the die. Can be tied to any voltage level. NC/18M N/A Not connected to t
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CY7C1292DV18 CY7C1294DV18 Byte Write Operations Programmable Impedance Byte Write operations are supported by the CY7C1292DV18. An external resistor, RQ, must be connected between the ZQ A Write operation is initiated as described in the Write Opera- pin on the SRAM and V to allow the SRAM to adjust its SS tions section above. The bytes that are written are determined output driver impedance. The value of RQ must be 5x the by BWS and BWS , which are sampled with each 18-bit data value of the i
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CY7C1292DV18 CY7C1294DV18 [1] Application Example R = 250οηµσ SRAM #1 SRAM #4 R = 250οηµσ ZQ ZQ R R W Vt W B B CQ/CQ# CQ/CQ# P P P P W W D Q D Q S S S S S S R A # CC# K K# A # # # CC# K K# # # DATA IN DATA OUT Vt Address Vt R RPS# BUS WPS# MASTER BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# Delayed K Delayed K# R R = 50οηµσ Vt = Vddq/2 [2, 3, 4, 5, 6, 7] Truth Table Operation K RPS WPS DQ DQ Write Cycle: L-H X L D(A + 0) at K(t) ↑ D(A + 1) at K(t) ↑ Load address on the rising edg
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CY7C1292DV18 CY7C1294DV18 [2, 8] Write Cycle Descriptions (CY7C1294DV18) BWS BWS BWS BWS KK Comments 0 1 2 3 L L L L L-H - During the Data portion of a Write sequence, all four bytes (D ) are written [35:0] into the device. L L L L - L-H During the Data portion of a Write sequence, all four bytes (D ) are written [35:0] into the device. L H H H L-H - During the Data portion of a Write sequence, only the lower byte (D ) is written [8:0] into the device. D will remain unaltered. [35:9] L H
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CY7C1292DV18 CY7C1294DV18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan test access register. This register is loaded when it is placed between the port (TAP) in the FBGA package. This part is fully compliant TDI and TDO pins as shown in TAP Controller Block Diagram. with IEEE Standard #1149.1-1900. The TAP operates using Upon power-up, the instruction register is loa
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CY7C1292DV18 CY7C1294DV18 IDCODE The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data The IDCODE instruction causes a vendor-specific, 32-bit code captured is shifted out, the preloaded data can be shifted in. to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows BYPASS the IDCODE to be shifted out of the device when the TAP When the BYPASS instruction is loaded in th
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CY7C1292DV18 CY7C1294DV18 [9] TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 001-00350 Rev. *A Page 11 of 23 [+] Feedback
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CY7C1292DV18 CY7C1294DV18 TAP Controller Block Diagram 0 Bypass Register Selection Selection Circuitry Circuitry 2 1 0 TDO TDI Instruction Register 29 31 30 . . 2 1 0 Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS [10, 11, 12] TAP Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit V Output HIGH Voltage I = −2.0 mA 1.4 V OH1 OH V Output HIGH Voltage I = −100 µA1.6 V OH2 OH V Output LOW Voltage I
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CY7C1292DV18 CY7C1294DV18 [13, 14] TAP AC Switching Characteristics Over the Operating Range Parameter Description Min. Max. Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Set-up Times t TMS Set-up to TCK Clock Rise 5 ns TMSS t TDI Set-up to TCK Clock Rise 5 ns TDIS t Capture Set-up to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TDI Hold after Clock Rise 5 ns TDIH t Capture Hold after Clock
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CY7C1292DV18 CY7C1294DV18 Identification Register Definitions Value Instruction Field CY7C1292DV18 CY7C1294DV18 Description Revision Number (31:29) 000 000 Version number. Cypress Device ID (28:12) 11010011010010110 11010011010100110 Defines the type of SRAM. Cypress JEDEC ID (11:1) 00000110100 00000110100 Unique identification of SRAM vendor. ID Register Presence (0) 1 1 Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary S
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CY7C1292DV18 CY7C1294DV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 26N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 57R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95 1N 15 9M 42 11B 69 3D 96 2M 16 9N 43
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~ ~ CY7C1292DV18 CY7C1294DV18 [16] DLL Constraints Power-Up Sequence in QDR-II SRAM • DLL uses K clock as its synchronizing input. The input QDR-II SRAMs must be powered up and initialized in a should have low phase jitter, which is specified as t . predefined manner to prevent undefined operations. KC Var • The DLL will function at frequencies down to 80 MHz. Power-Up Sequence • If the input clock is unstable and the DLL is enabled, then • Apply power with DOFF tied HIGH (All other inputs can
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CY7C1292DV18 CY7C1294DV18 Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage.......................................... > 2001V (Above which the useful life may be impaired.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current.................................................... > 200 mA Ambient Temperature with Operating Range Power Applied.............................
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CY7C1292DV18 CY7C1294DV18 [21] Thermal Resistance Parameter Description Test Conditions 165 FBGA Unit Θ Thermal Resistance (Junction to Ambient) Test conditions follow standard test 28.51 °C/W JA methods and procedures for measuring Θ Thermal Resistance (Junction to Case) 5.91 °C/W JC thermal impedance, per EIA/JESD51. AC Test Loads and Waveforms V = 0.75V REF 0.75V V REF V 0.75V REF R = 50Ω OUTPUT [22] ALL INPUT PULSES Z = 50Ω 0 OUTPUT 1.25V Device R = 50Ω L 0.75V Under Device 0.25V Test 5p
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CY7C1292DV18 CY7C1294DV18 [22, 23] Switching Characteristics Over the Operating Range 250 MHz 200 MHz 167 MHz Cypress Consortium Parameter Parameter Description Min. Max. Min. Max. Min. Max. Unit [24] t t V (Typical) to the first Access 11 1 ms POWER KHKH DD t t K Clock and C Clock Cycle Time 4.0 6.3 5.0 7.9 6.0 7.9 ns CYC KHKL t t 1.6 – 2.0 – 2.4 – ns Input Clock (K/K and C/C) HIGH KH KLKH t t 1.6 – 2.0 – 2.4 – ns Input Clock (K/K and C/C) LOW KL KHKH K Clock Rise to K Clock Rise and C to C
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CY7C1292DV18 CY7C1294DV18 [27, 28, 29] Switching Waveforms Read/Write/Deselect Sequence READ WRITE READ WRITE READ WRITE NOP WRITE NOP 12 3458 6 7 9 10 K t t t t KH KL CYC KHKH K RPS tt t SC HC WPS A0 A1 A2 A3 A4 A A5 A6 t t t t SA HA SA HA D D10 D11 D30 D31 D50 D51 D60 D61 t t t t SD HD SD HD Q Q00 Q01 Q20 Q21 Q40 Q41 t t CLZ CQDOH t t CHZ DOH t KHCH t t KL CO t CQD t C KH t t KHKH CYC t KHCH C t CCQO t CQOH CQ t CCQO t CQOH CQ DON’T CARE UNDEFINED Notes: 27. Q00 refers to output from addre
