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CY7C1223H
2-Mbit (128K x 18) Pipelined DCD Sync SRAM
[1]
Features Functional Description
• Registered inputs and outputs for pipelined operation The CY7C1223H SRAM integrates 128K x 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
• Optimal for performance (Double-Cycle deselect)
counter for internal burst operation. All synchronous inputs are
— Depth expansion without wait state
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchrono
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CY7C1223H Logic Block Diagram ADDRESS A0,A1,A REGISTER 2 A[1:0] MODE ADV Q1 BURST CLK COUNTER AND LOGIC CLR Q0 ADSC ADSP DQB , DQPB DQB, DQPB BYTE BYTE WRITE DRIVER OUTPUT BWB OUTPUT DQs WRITE REGISTER SENSE MEMORY BUFFERS REGISTERS DQPA AMPS ARRAY DQA, DQPA DQPB E DQA , DQPA BYTE BYTE BWA WRITE DRIVER WRITE REGISTER BWE INPUT GW REGISTERS ENABLE CE1 PIPELINED REGISTER CE2 ENABLE CE3 OE SLEEP ZZ CONTROL Document #: 38-05674 Rev. *B Page 2 of 16 [+] Feedback
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CY7C1223H Pin Configurations 100-pin TQFP Pinout Top View NC 1 80 A NC 2 79 NC NC 3 78 NC V DDQ 4 77 V DDQ V SSQ 5 76 V SSQ NC 6 75 NC NC 7 74 DQP A DQ 8 73 B DQ A DQ 9 72 DQ B A 10 V 71 V SSQ SSQ V 11 70 DDQ V DDQ 12 DQ 69 DQ B A DQ 13 68 DQ B A NC 14 67 V SS 15 V 66 DD CY7C1223H NC 16 NC 65 V DD 17 V 64 SS ZZ 18 DQ 63 DQ B A DQ 19 62 DQ B A V 20 61 V DDQ DDQ 21 V 60 V SSQ SSQ 22 DQ 59 DQ B A DQ 23 58 DQ B A 24 DQP 57 NC B 25 NC 56 NC V SSQ 26 55 V SSQ V DDQ 27 54 V DDQ 28 NC 53 NC NC 29 52
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CY7C1223H Pin Descriptions Pin Type Description A0, A , A Input- Address Inputs used to select one of the 128K address locations. Sampled at the rising 1 Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. 1 2 3 A are fed to the two-bit counter. [1:0] BW Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. [A:B] Synchronous Sampled on the rising edge of CLK. GW Input- Global Write Enable Input, ac
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CY7C1223H then the write operation is controlled by BWE and BW Functional Overview [A:B] signals. The CY7C1223H provides Byte Write capability that All synchronous inputs pass through input registers controlled is described in the Write Cycle Description table. Asserting the by the rising edge of the clock. All data outputs pass through Byte Write Enable input (BWE) with the selected Byte Write output registers controlled by the rising edge of the clock. input will selectively write to only the
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CY7C1223H Linear Burst Address Table (MODE = GND) Interleaved Burst Address Table (MODE = Floating or V ) DD First Second Third Fourth First Second Third Fourth Address Address Address Address Address Address Address Address A1, A0 A1, A0 A1, A0 A1, A0 A1, A0 A1, A0 A1, A0 A1, A0 00 01 10 11 00 01 10 11 01 10 11 00 01 00 11 10 10 11 00 01 10 11 00 01 11 00 01 10 11 10 01 00 [2, 3, 4, 5, 6] Truth Table Address Operation Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 Deselected Cycle,
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CY7C1223H [2, 3] Truth Table for Read/Write Function GW BWE BW BW A B Read H H X X Read H L H H Write byte A - (DQ and DQP)H L L H A A Write byte B- (DQ and DQP)H L H L B B Write all bytes H L L L Write all bytes L X X X ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I Sleep mode standby current ZZ > V − 0.2V 40 mA DDZZ DD t Device operation to ZZ ZZ > V − 0.2V 2t ns ZZS DD CYC t ZZ recovery time ZZ < 0.2V 2t ns ZZREC CYC t ZZ Active to sleep current This
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CY7C1223H DC Input Voltage ..................................... –0.5V to V +0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage........................................... > 2001V lines, not tested.) (per MIL-STD-883,Method 3015) Storage Temperature .................................... –65°C to +150° Latch-up Current................................................
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CY7C1223H [9] Capacitance 100 TQFP Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 3.3V DD C Clock Input Capacitance 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 pF I/O [9] Thermal Characteristics 100 TQFP Parameter Description Test Conditions Package Unit Θ Thermal Resistance Test conditions follow standard 30.32 °C/W JA (Junction to Ambient) test methods and procedures for measuring thermal impedance, Θ Thermal Resistance 6.85 °C
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CY7C1223H [14, 15] Switching Characteristics Over the Operating Range 166 MHz 133 MHz Parameter Description Min. Max. Min. Max. Unit [10] t V (Typical) to the first Access 11 ms POWER DD Clock t Clock Cycle Time 6.0 7.5 ns CYC t Clock HIGH 2.5 3.0 ns CH t Clock LOW 2.5 3.0 ns CL Output Times t Data Output Valid After CLK Rise 3.5 4.0 ns CO t Data Output Hold After CLK Rise 1.5 1.5 ns DOH [11, 12, 13] t Clock to Low-Z 00 ns CLZ [11, 12, 13] t Clock to High-Z 3.5 4.0 ns CHZ t OE LOW to Outpu
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CY7C1223H Switching Waveforms [16] Read Timing t CYC CLK t t CH CL t t ADS ADH ADSP t t ADS ADH ADSC t t AS AH ADDRESS A1 A2 A3 Burst continued with t t WES WEH new base address GW, BWE,BW [A:B] Deselect t t CES CEH cycle CE t t ADVS ADVH ADV ADV suspends burst OE t t OEV CO t t t t CHZ t OELZ OEHZ DOH CLZ Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) Data Out (Q) Q(A1) High-Z t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 16. On this
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CY7C1223H Switching Waveforms (continued) [16, 17] Write Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC extends burst t t ADH ADS t t ADS ADH ADSC t t AH AS A1 A2 A3 ADDRESS Byte write signals are ignored for first cycle when t t ADSP initiates burst WES WEH BWE, BW[A:B] t t WES WEH GW t t CES CEH CE t t ADVH ADVS ADV ADV suspends burst OE t t DS DH D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) High-Z D(A1) Data in (D) t OEHZ Data Out (Q) BURST READ Single WRITE BUR
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CY7C1223H Switching Waveforms (continued) [16, 18, 19] Read/Write Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC t t AS AH ADDRESS A1 A2 A3 A4 A5 A6 t t WEH WES BWE, BW[A:B] t t CES CEH CE ADV OE t t t CO DS DH t OELZ Data In (D) D(A3) D(A5) D(A6) High-Z t t OEHZ CLZ Data Out (Q) Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) High-Z Back-to-Back READs Single WRITE BURST READ Back-to-Back WRITEs DON’T CARE UNDEFINED Notes: 18. The data bus (Q) remains in High-Z following a Write cycle, unless a
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CY7C1223H Switching Waveforms (continued) [20,21] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 20. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 21. DQs are in High-Z when exiting ZZ sleep mode. Document #: 38-05674 Rev. *B Page 14 of 16 [+] Feedback
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CY7C1223H Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 166 CY7C1223H-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1223H-166AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial 133 CY7C1223H-133AXC 51-85050 100
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CY7C1223H Document History Page Document Title: CY7C1223H 2-Mbit (128K x 18) Pipelined DCD Sync SRAM Document Number: 38-05674 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 347357 See ECN PCI New Data Sheet *A 424820 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed Three-State to Tri-State. Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteri
