Summary of the content on the page No. 1
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through
SRAM with NoBL™ Architecture
Features
Functional Description
■ No Bus Latency™ (NoBL™) architecture eliminates dead
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
cycles between write and read cycles
are 3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through
burst SRAMs designed specifically to support unlimited true
■ Supports up to 133 MHz bus operations with zero wait states
back-to-back read or write op
Summary of the content on the page No. 2
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Logic Block Diagram – CY7C1471BV33 (2M x 36) ADDRESS A0, A1, A A1 REGISTER A1' D1 Q1 A0 A0' D0 Q0 MODE BURST CE ADV/LD LOGIC CLK C C CEN WRITE ADDRESS REGISTER O U T P D S A U E T T ADV/LD N A S B MEMORY BW A WRITE E U WRITE REGISTRY S ARRAY DQs DRIVERS F BW B AND DATA COHERENCY T DQP A A F E CONTROL LOGIC DQP B BW C M E E DQP C P R R BW D DQP D S S I WE E N G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram – CY7C1473BV33 (4
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Logic Block Diagram – CY7C1475BV33 (1M x 72) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E U A ADV/LD T N T T S BW a A R MEMORY E B WRITE E DQ s BW b ARRAY S U G DRIVERS BW c A T F DQ Pa WRITE REGISTRY I M F E AND DATA COHERENCY BW d S DQ Pb P E E CONTROL LOGIC T S R R BW e DQ Pc E S I R DQ Pd BW f N S G BW g DQ Pe E E BW h DQ Pf DQ Pg DQ
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Pin Configuration Figure 1. 100-Pin TQFP Pinout DQP 80 1 DQP C B DQ 79 C 2 DQ B DQ 78 3 DQ C B V 77 4 DDQ V DDQ V 76 5 V SS SS DQ 75 6 C DQ BYTE C B BYTE B DQ 74 7 DQ C B DQ 73 8 C DQ B DQ 72 9 DQ C B V 71 10 SS V SS V 70 11 V DDQ DDQ DQ 69 12 C DQ B DQ 68 13 DQ C B CY7C1471BV33 NC 67 14 V SS V 66 15 NC DD NC 65 16 V DD V 64 ZZ 17 SS DQ 63 18 D DQ A DQ 62 D 19 DQ A V 61 20 DDQ V DDQ V 60 SS 21 V SS DQ 59 22 D DQ A DQ 58 D 23 DQ BYTE D A BYTE A DQ 57 24
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Pin Configuration (continued) Figure 2. 100-Pin TQFP Pinout NC 80 1 A NC 79 2 NC NC 78 3 NC V 77 4 DDQ V DDQ V 76 5 V SS SS NC 75 6 NC NC 74 7 DQP A DQ 73 8 B DQ A DQ 72 9 DQ B A V 71 10 SS V SS V 70 11 V DDQ DDQ DQ 69 12 B DQ A DQ 68 13 DQ B A CY7C1473BV33 NC 67 14 V SS BYTE A V 66 15 NC DD BYTE B NC 65 16 V DD V 64 ZZ 17 SS DQ 63 18 B DQ A DQ 62 B 19 DQ A V 61 20 DDQ V DDQ V 60 SS 21 V SS DQ 59 22 B DQ A DQ 58 B 23 DQ A DQP 57 24 NC B NC 56 25 NC V 55
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Pin Configuration (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471BV33 (2M x 36) 1 234 5 6 7 89 10 11 NC/576M CE BW BW CE CEN ADV/LD A A NC A A 1 C B 3 NC/1G A CE2 BW BW CLK WE OE A A NC B D A C DQP NC V V V V V V V NC DQP C DDQ SS SS SS SS SS DDQ B D DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B E DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ F C DD SS DD B C DDQ SS SS DDQ B DQ DQ V V V V V V V
Summary of the content on the page No. 7
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Pin Configuration (continued) 209-Ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1475BV33 (1M × 72) 1 2 3 4 567 8 9 10 11 A DQg DQgAA CE ADV/LDA CEA DQb DQb 2 3 DQg DQg BWS BWS NC WE A BWS BWS DQb DQb B c g b f C DQg DQg BWS BWS NC/576M CE NC BWS BWS DQb DQb h d 1 e a D DQg NC DQg V NC/1G OE NC V SS NC DQb SS DQb E DQPg DQPc V V V V V V V DDQ DDQ DD DD DD DDQ DDQ DQPf DQPb F DQc DQc V V V V NC V DQf V SS SS SS SS SS DQf SS G DQc V DQc V V V NC DD V V DDQ DDQ DQ
Summary of the content on the page No. 8
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Pin Definitions Name IO Description A , A , A Input- Address Inputs used to select one of the Address Locations. Sampled at the rising edge 0 1 Synchronous of the CLK. A is fed to the two-bit burst counter. [1:0] BW , BW , Input- Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled A B BW , BW , Synchronous on the rising edge of CLK. C D BW , BW , E F BW , BW G H WE Input- Write Enable Input, Active LOW. Sampled on th
Summary of the content on the page No. 9
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Pin Definitions (continued) Name IO Description TDO JTAG serial Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG output feature is not used, this pin must be left unconnected. This pin is not available on TQFP Synchronous packages. TDI JTAG serial input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not used, this pin can be left floating or connected t
Summary of the content on the page No. 10
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 subsequent clock rise, the Chip Enables (CE , CE , and CE ) Single Write Accesses 1 2 3 and WE inputs are ignored and the burst counter is incremented. Write accesses are initiated when the following conditions are Drive the correct BW inputs in each cycle of the burst write to X satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE , 1 2 write the correct bytes of data. and CE are all asserted active, and (3) WE is asserted LOW. 3 The address pre
Summary of the content on the page No. 11
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 [1, 2, 3, 4, 5, 6, 7] The truth table for CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 follows. Truth Table Address Operation CE CE ZZ ADV/LD WE BW OE CEN CLK DQ CE 1 2 X 3 Used Deselect Cycle None H X X L L X X X L L->H Tri-State Deselect Cycle None X X H L L X X X L L->H Tri-State Deselect Cycle None X L X L L X X X L L->H Tri-State Continue Deselect Cycle None X X X L H X X X L L->H Tri-State Read Cycle External L H L L L H X L L L->H Data Out (Q) (Be
Summary of the content on the page No. 12
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 [1, 2, 8] The read/write truth table for CY7C1471BV33 follows. Truth Table for Read/Write Function WE BW BW BW BW A B C D Read H X X X X Write No bytes written L HHHH Write Byte A – (DQ and DQP) L L HHH A A Write Byte B – (DQ and DQP)LHLHH B B Write Byte C – (DQ and DQP)LHHLH C C Write Byte D – (DQ and DQP) L HHH L D D Write All Bytes L L L L L [1, 2, 8] The read/write truth table for CY7C1473BV33 follows. Truth Table for Read/Write Function WE BW BW a
Summary of the content on the page No. 13
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Performing a TAP Reset IEEE 1149.1 Serial Boundary Scan (JTAG) A RESET is performed by forcing TMS HIGH (V ) for five rising DD The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 edges of TCK. This RESET does not affect the operation of the incorporate a serial boundary scan test access port (TAP). This SRAM and may be performed while the SRAM is operating. port operates in accordance with IEEE Standard 1149.1-1990 During power up, the TAP is reset internall
Summary of the content on the page No. 14
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 SAMPLE/PRELOAD TAP Instruction Set SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The Overview PRELOAD portion of this instruction is not implemented, so the Eight different instructions are possible with the three-bit device TAP controller is not fully 1149.1 compliant. instruction register. All combinations are listed in “Identification When the SAMPLE/PRELOAD instruction is loaded into the Codes” on page 19. Three of these instructions are listed as
Summary of the content on the page No. 15
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 1 1 RUN-TEST/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 PAUSE-DR 0 PAUSE-IR 0 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 0 1 0 Document #: 001-15029 Rev. *B Page 15 of 32 [+] Feedback
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Selection Instruction Register TDI TDO Circuitry Circuitry 31 30 29 . . . 2 1 0 Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TAP CONTROLLER TM S Document #: 001-15029 Rev. *B Page 16 of 32 [+] Feedback
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels .................................................V to 3.3V Input pulse levels ................................................ V to 2.5V SS SS Input rise and fall times................................................... 1 ns Input rise and fall time..................................................... 1 ns Input timing reference levels...........................................1.5V
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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 TAP AC Switching Characteristics [10, 11] Over the Operating Range Parameter Description Min Max Unit Clock t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH time 20 ns TH t TCK Clock LOW time 20 ns TL Output Times t TCK Clock LOW to TDO Valid 5 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hol
Summary of the content on the page No. 19
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Identification Register Definitions CY7C1471BV33 CY7C1473BV33 CY7C1475BV33 Instruction Field Description (2Mx36) (4Mx18) (1Mx72) Revision Number (31:29) 000 000 000 Describes the version number [12] Device Depth (28:24) 01011 01011 01011 Reserved for internal use Architecture/Memory Type(23:18) 001001 001001 001001 Defines memory type and architecture Bus Width/Density(17:12) 100100 010100 110100 Defines width and density Cypress JEDEC ID Code (11:1) 00000
Summary of the content on the page No. 20
CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1C1 21 R3 41 J11 61 B7 2 D1 22 P2 42 K10 62 B6 3 E1 23 R4 43 J10 63 A6 4D2 24 P6 44 H11 64 B5 5E2 25 R6 45 G11 65 A5 6F1 26 R8 46 F11 66 A4 7G1 27 P3 47 E11 67 B4 8 F2 28 P4 48 D10 68 B3 9G2 29 P8 49 D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56
