Cypress CY7C68015A user manual

User manual for the device Cypress CY7C68015A

Device: Cypress CY7C68015A
Category: Computer Hardware
Manufacturer: Cypress
Size: 1.76 MB
Added : 6/27/2014
Number of pages: 62
Print the manual

Download

How to use this site?

Our goal is to provide you with a quick access to the content of the user manual for Cypress CY7C68015A. Using the online preview, you can quickly view the contents and go to the page where you will find the solution to your problem with Cypress CY7C68015A.

For your convenience

If looking through the Cypress CY7C68015A user manual directly on this website is not convenient for you, there are two possible solutions:

  • Full Screen Viewing - to easily view the user manual (without downloading it to your computer), you can use full-screen viewing mode. To start viewing the user manual Cypress CY7C68015A on full screen, use the button Fullscreen.
  • Downloading to your computer - You can also download the user manual Cypress CY7C68015A to your computer and keep it in your files. However, if you do not want to take up too much of your disk space, you can always download it in the future from ManualsBase.
Cypress CY7C68015A User manual - Online PDF
Advertisement
« Page 1 of 62 »
Advertisement
Print version

Many people prefer to read the documents not on the screen, but in the printed version. The option to print the manual has also been provided, and you can use it by clicking the link above - Print the manual. You do not have to print the entire manual Cypress CY7C68015A but the selected pages only. paper.

Summaries

Below you will find previews of the content of the user manuals presented on the following pages to Cypress CY7C68015A. If you want to quickly view the content of pages found on the following pages of the manual, you can use them.

Abstracts of contents
Summary of the content on the page No. 1

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
EZ-USB FX2LP™ USB Microcontroller
High-Speed USB Peripheral Controller
■ GPIF (General Programmable Interface)
1. Features (CY7C68013A/14A/15A/16A)
❐ Enables direct connection to most parallel interfaces
■ USB 2.0 USB IF high-speed certified (TID # 40460272)
❐ Programmable waveform descriptors and configuration reg-
isters to define waveforms
■ Single chip integrated USB 2.0 transceiver, smart SIE, and
❐ Supports multiple Ready (RDY) inputs and Co

Summary of the content on the page No. 2

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Lo Logic Block Diagram gic Block Diagram High performance micro 24 MHz using standard tools Ext. XTAL with lower-power options FX2LP 2 /0.5 I C 8051 Core x20 Master VCC /1.0 12/24/48 MHz, PLL /2.0 four clocks/cycle Abundant IO Additional IOs (24) 1.5k including two USARTS connected for full-speed General ADDR (9) programmable I/F D+ to ASIC/DSP or bus GPIF USB standards such as CY 16 KB RDY (6) 2.0 CTL (6) ATAPI, EPP, etc. Smart D– RAM ECC XCVR USB

Summary of the content on the page No. 3

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A frequency is 12 MHz. The clock frequency of the 8051 can be 2. Applications changed by the 8051 through the CPUCS register, dynamically. ■ Portable video recorder Figure 1. Crystal Configuration ■ MPEG/TV conversion 24 MHz C1 C2 ■ DSL modems ■ ATA interface 12 pf 12 pf ■ Memory card readers ■ Legacy conversion devices 20 × PLL ■ Cameras ■ Scanners 12-pF capacitor values assumes a trace capacitance of 3 pF per side on a four-layer FR4 PCA ■ Home PNA

Summary of the content on the page No. 4

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 1. Special Function Registers x 8x 9x Ax Bx Cx Dx Ex Fx 0 IOA IOB IOC IOD SCON1 PSW ACC B 1SP EXIF INT2CLR IOE SBUF1 2DPL0 MPAGE INT4CLR OEA 3DPH0 OEB 4 DPL1 OEC 5 DPH1 OED 6 DPS OEE 7PCON 8 TCON SCON0 IE IP T2CON EICON EIE EIP 9 TMOD SBUF0 ATL0 AUTOPTRH1 EP2468STAT EP01STAT RCAP2L BTL1 AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H CTH0 reserved EP68FIFOFLGS TL2 DTH1 AUTOPTRH2 GPIFSGLDATH TH2 E CKCON AUTOPTRL2 GPIFSGLDATLX F reserved AUTOPTRSET-UP GP

Summary of the content on the page No. 5

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A The FX2LP jump instruction is encoded as follows: Table 3. INT2 USB Interrupts USB INTERRUPT TABLE FOR INT2 Priority INT2VEC Value Source Notes 1 00 SUDAV Setup Data Available 2 04 SOF Start of Frame (or microframe) 3 08 SUTOK Setup Token Received 4 0C SUSPEND USB Suspend request 5 10 USB RESET Bus reset 6 14 HISPEED Entered high-speed operation 7 18 EP0ACK FX2LP ACK’d the CONTROL Handshake 8 1C reserved 9 20 EP0-IN EP0-IN ready to be loaded with d

Summary of the content on the page No. 6

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Table 4. Individual FIFO/GPIF Interrupt Sources Priority INT4VEC Value Source Notes 1 80 EP2PF Endpoint 2 Programmable Flag 2 84 EP4PF Endpoint 4 Programmable Flag 3 88 EP6PF Endpoint 6 Programmable Flag 4 8C EP8PF Endpoint 8 Programmable Flag 5 90 EP2EF Endpoint 2 Empty Flag 6 94 EP4EF Endpoint 4 Empty Flag 7 98 EP6EF Endpoint 6 Empty Flag 8 9C EP8EF Endpoint 8 Empty Flag 9 A0 EP2FF Endpoint 2 Full Flag 10 A4 EP4FF Endpoint 4 Full Flag 11 A8 EP6FF

Summary of the content on the page No. 7

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 2. Reset Timing Plots RESET# RESET# V IL V IL 3.3V 3.3V 3.0V VCC VCC 0V 0V T T RESET RESET Power on Reset Powered Reset Table 5. Reset Timing Values 3.10 Program/Data RAM Condition T 3.10.1 Size RESET Power on Reset with Crystal 5 ms The FX2LP has 16 KBytes of internal program/data RAM, where PSEN#/RD# signals are internally ORed to enable the 8051 to Power on Reset with External 200 μs + Clock stability time access it as both program a

Summary of the content on the page No. 8

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3. Internal Code Memory, EA = 0 Inside FX2LP Outside FX2LP FFFF 7.5 KBytes (OK to populate USB regs and 4K FIFO buffers data memory here—RD#/WR# (RD#,WR#) strobes are not E200 E1FF active) 0.5 KBytes RAM Data (RD#,WR#)* E000 48 KBytes External 40 KBytes Code External Memory Data (PSEN#) Memory (RD#,WR#) 3FFF (Ok to populate (OK to populate data memory program 16 KBytes RAM here—RD#/WR# memory here— Code and Data strobes are not PSEN# strobe (

Summary of the content on the page No. 9

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 4. External Code Memory, EA = 1 Inside FX2LP Outside FX2LP FFFF 7.5 KBytes (OK to populate USB regs and data memory 4K FIFO buffers (RD#,WR#) here—RD#/WR# strobes are not E200 active) E1FF 0.5 KBytes RAM Data (RD#,WR#)* E000 40 KBytes External 64 KBytes Data Memory External (RD#,WR#) Code Memory (PSEN#) 3FFF (Ok to populate 16 KBytes data memory RAM here—RD#/WR# Data strobes are not (RD#,WR#)* active) 0000 Data Code 2 *SUDPTR, USB upload/down

Summary of the content on the page No. 10

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3.12.3 Setup Data Buffer 3.12 Endpoint RAM A separate 8 byte buffer at 0xE6B8-0xE6BF holds the setup data 3.12.1 Size from a CONTROL transfer. ■ 3× 64 bytes (Endpoints 0 and 1) 3.12.4 Endpoint Configurations (High -speed Mode) ■ 8 × 512 bytes (Endpoints 2, 4, 6, 8) Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either 3.12.2 Organization BULK or INTERRUPT. ■ EP0 The endpoin

Summary of the content on the page No. 11

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3.12.5 Default Full-Speed Alternate Settings [4, 5] Table 6. Default Full-Speed Alternate Settings Alternate Setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 64 bulk 64 int 64 int ep1in 0 64 bulk 64 int 64 int ep2 0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×) ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×) ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×) ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×) 3.12.6 Default High-Speed Alte

Summary of the content on the page No. 12

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [7] 3.13.3 GPIF and FIFO Clock Rates 3.15 ECC Generation An 8051 register bit selects one of two frequencies for the inter- The EZ-USB can calculate ECCs (Error Correcting Codes) on nally supplied interface clock: 30 MHz and 48 MHz. Alternatively, data that passes across its GPIF or Slave FIFO interfaces. There an externally supplied clock of 5 MHz–48 MHz feeding the IFCLK are two ECC configurations: Two ECCs, each calculated over pin can be used a

Summary of the content on the page No. 13

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2 2 3.18.2 I C Interface Boot Load Access 3.18 I C Controller 2 2 At power on reset the I C interface boot loader loads the FX2LP has one I C port that is driven by two internal controllers, VID/PID/DID configuration bytes and up to 16 KBytes of one that automatically operates at boot time to load VID/PID/DID program/data. The available RAM spaces are 16 KBytes from and configuration information, and another that the 8051 uses 2 2 0x0000–0x3FFF and

Summary of the content on the page No. 14

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3.20 CY7C68013A/14A and CY7C68015A/16A 4. Pin Assignments Differences Figure 6 on page 15 identifies all signals for the five package CY7C68013A is identical to CY7C68014A in form, fit, and types. The following pages illustrate the individual pin diagrams, functionality. CY7C68015A is identical to CY7C68016A in form, plus a combination diagram showing which of the full set of fit, and functionality. CY7C68014A and CY7C68016A have a signals are ava

Summary of the content on the page No. 15

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 6. Signal Port GPIF Master Slave FIFO PD7 FD[15] FD[15] PD6 FD[14] FD[14] PD5 FD[13] FD[13] PD4 FD[12] FD[12] PD3 FD[11] FD[11] PD2 FD[10] FD[10] PD1 FD[9] FD[9] PD0 FD[8] FD[8] PB7 FD[7] FD[7] PB6 FD[6] FD[6] PB5 FD[5] FD[5] XTALIN PB4 FD[4] FD[4] XTALOUT PB3 FD[3] FD[3] RESET# PB2 FD[2] FD[2] WAKEUP# PB1 FD[1] FD[1] PB0 FD[0] FD[0] SCL 56 SDA RDY0 SLRD RDY1 SLWR **PE0 replaces IFCLK & PE1 replaces CLKOUT CTL0 FLAGA on CY7C68015A/16A CTL1 F

Summary of the content on the page No. 16

PD1/FD9 VCC 103 64 D4 104 PD2/FD10 63 D3 105 PD3/FD11 62 106 INT5# D2 61 107 VCC D1 60 108 PE0/T0OUT D0 59 GND 109 PE1/T1OUT 58 PB7/FD7 110 PE2/T2OUT 57 111 PE3/RXD0OUT PB6/FD6 56 112 PE4/RXD1OUT PB5/FD5 55 113 PE5/INT6 PB4/FD4 54 114 RXD1 PE6/T2EX 53 TXD1 115 PE7/GPIFADR8 52 116 GND RXD0 51 117 A4 TXD0 50 118 A5 GND 49 119 VCC 48 A6 120 PB3/FD3 A7 47 121 PD4/FD12 PB2/FD2 46 122 PD5/FD13 PB1/FD1 45 123 PD6/FD14 PB0/FD0 44 124 VCC 43 PD7/FD15 125 CS# 42 GND 126 41 A8 WR# 127 A9 RD# 40 128 A10 PSE

Summary of the content on the page No. 17

GND 81 PD1/FD9 50 VCC 82 PD2/FD10 49 GND 83 48 PD3/FD11 84 PB7/FD7 47 INT5# 85 PB6/FD6 46 VCC 86 PB5/FD5 45 PE0/T0OUT PB4/FD4 87 PE1/T1OUT 44 RXD1 88 43 PE2/T2OUT 89 TXD1 42 PE3/RXD0OUT 90 RXD0 41 PE4/RXD1OUT 91 TXD0 40 PE5/INT6 92 GND 39 PE6/T2EX 93 38 VCC PE7/GPIFADR8 94 PB3/FD3 37 GND 95 PB2/FD2 36 PD4/FD12 96 PB1/FD1 35 PD5/FD13 97 PB0/FD0 34 PD6/FD14 98 33 VCC PD7/FD15 99 32 WR# GND 100 RD# 31 CLKOUT CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 8. CY7C68013A/CY7C68014A 100-pin TQFP

Summary of the content on the page No. 18

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 9. CY7C68013A/CY7C68014A 56-pin SSOP Pin Assignment CY7C68013A/CY7C68014A 56-pin SSOP 1 56 PD5/FD13 PD4/FD12 2 55 PD6/FD14 PD3/FD11 3 PD7/FD15 PD2/FD10 54 4 GND PD1/FD9 53 5 52 CLKOUT PD0/FD8 6 51 VCC *WAKEUP 7 50 GND VCC 8 RDY0/*SLRD RESET# 49 9 RDY1/*SLWR GND 48 10 47 AVCC PA7/*FLAGD/SLCS# 11 46 XTALOUT PA6/PKTEND 12 45 XTALIN PA5/FIFOADR1 13 AGND PA4/FIFOADR0 44 14 AVCC PA3/*WU2 43 15 42 DPLUS PA2/*SLOE 16 41 DMINUS PA1/INT1# 17 40 AGND PA

Summary of the content on the page No. 19

GND VCC 43 28 VCC *WAKEUP 44 27 GND PD0/FD8 45 26 PB7/FD7 PD1/FD9 46 25 PB6/FD6 PD2/FD10 47 24 PB5/FD5 PD3/FD11 48 23 PB4/FD4 PD4/FD12 49 22 PB3/FD3 PD5/FD13 50 21 PB2/FD2 PD6/FD14 51 20 PB1/FD1 PD7/FD15 52 19 PB0/FD0 GND 53 18 VCC CLKOUT/**PE1 54 17 SDA VCC 55 16 56 15 SCL GND CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 10. CY7C68013A/14A/15A/16A 56-pin QFN Pin Assignment RESET# RDY0/*SLRD 1 42 GND RDY1/*SLWR 2 41 PA7/*FLAGD/SLCS# AVCC 3 40 PA6/*PKTEND XTALOUT 4 39 CY7C68013A/CY7C6801

Summary of the content on the page No. 20

CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 11. CY7C68013A 56-pin VFBGA Pin Assignment - Top View 12 34 5 678 A 1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B B 1C 2C 3C 4C 5C 6C 7C 8C C 1D 2D 7D 8D D E 1E 2E 7E 8E F 1F 2F 3F 4F 5F 6F 7F 8F 1G 2G 3G 4G 5G 6G 7G 8G G 1H 2H 3H 4H 5H 6H 7H 8H H Document #: 38-08032 Rev. *L Page 20 of 62 [+] Feedback [+] Feedback


Alternative user manuals
# User manual Category Download
1 Cypress CapSense CY8C20x36 User manual Computer Hardware 0
2 Cypress CY14B101L User manual Computer Hardware 0
3 Cypress CY14B101LA User manual Computer Hardware 0
4 Cypress CY14B104N User manual Computer Hardware 0
5 Cypress AutoStore STK14CA8 User manual Computer Hardware 0
6 Cypress CY14B101Q2 User manual Computer Hardware 0
7 Cypress CY14B104L User manual Computer Hardware 0
8 Cypress CY2048WAF User manual Computer Hardware 0
9 Cypress CY14B108L User manual Computer Hardware 0
10 Cypress 7C185-15 User manual Computer Hardware 0
11 Cypress CY14B104NA User manual Computer Hardware 0
12 Cypress CY14B104M User manual Computer Hardware 0
13 Cypress AutoStore STK17TA8 User manual Computer Hardware 0
14 Cypress CY62158E User manual Computer Hardware 0
15 Cypress CY14B256L User manual Computer Hardware 0
16 Sony MSAKIT-PC4A User manual Computer Hardware 2
17 Sony MRW62E-S1 2694866142 User manual Computer Hardware 5
18 Philips MATCH LINE 9596 User manual Computer Hardware 17
19 Sony 64GB SDHC Class 10 Memory Card Readers SF32UY User manual Computer Hardware 1
20 Philips PSC702 User manual Computer Hardware 1