Summary of the content on the page No. 1
MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
Low Supply Voltage Range 1.8 V – 3.6 V Serial Onboard Programming
Ultralow-Power Consumption Programmable Code Protection by Security
Low Operation Current, Fuse (C11x1 Only)
1.3 m A at 4 kHz, 2.2 V
Family Members Include:
160 m A at 1 MHz, 2.2 V
MSP430C1111: 2KB ROM,128B RAM
Five Power Saving Modes: MSP430C1121: 4KB ROM, 256B RAM
(Standby Mode: 0.8 m A, MSP430F1101: 1KB + 128B Flash Memory
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 AVAILABLE OPTIONS PACKAGED DEVICES PLASTIC PLASTIC T A 20-PIN SOWB 20-PIN TSSOP (DW) (PW) MSP430C1111IDW MSP430F1101IPW MSP430C1121IDW MSP430F1121IPW –40 40° °Ct C to o8 85 5° °C C MSP430F1101IDW MSP430F1121IDW functional block diagram V V XIN XOUT RST/NMI P1.0–7 CC SS 8 1/2/4 KB ROM/ Outx ACLK Oscillator I/O Port P1 JTAG Rosc 128/256B Power-on- Flash+126/256B CCIxA System Clock SMCLK 8 I/O’s, All With Flash I
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 Terminal Functions TERMINAL TERMINAL I/O I/O DESCRIPTION DESCRIPTION NAME NO. P1.0/TACLK 13 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input P1.1/TA0 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output P1.2/TA1 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 16 I/O General-purpose digital I/O pin/Tim
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 short-form description (continued) PC/R0 Program Counter CPU All sixteen registers are located inside the CPU, SP/R1 Stack Pointer providing reduced instruction execution time. This reduces a register-register operation execution Status Register SR/CG1/R2 time to one cycle of the processor. Constant Generator CG2/R3 Four registers are reserved for special use as a program counter, a stack pointer, a status reg
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 instruction set (continued) Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other instructions. These addressing modes provide indirect addressing, ideally suited for computed branches and calls. The full use of this programming capability permits a program structure different from conventional 8- and 16-bit controllers. For example, numerous routines can ea
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 status register R2 15 9 8 7 65 43 21 0 Reserved For Future V SCG1 SCG0 OscOff CPUOff GIE N Z C Enhancements rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 The bits CPUOff, SCG1, SCG0, and OscOff are the most important low-power control bits when the basic function of the system clock generator is established. They are pushed onto the stack whenever an interrupt is accepted and thereby saved so that the prev
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the memory with an address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY WDTIFG (Note1) Power-up, external reset, watchdog Reset 0FFFEh 15, highest KEYV (Note 1) (non)-
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 76 5 4 32 1 0 Address 0h OFIE WDTIE ACCVIE NMIIE rw-0 rw-0 rw-0 rw-0 WDTIE: Watchdog timer enable si
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 memory organization MSP430C1111 MSP430C1121 MSP430F1101 MSP430F1121 FFFFh FFFFh FFFFh FFFFh Int. Vector Int. Vector Int. Vector Int. Vector FFE0h FFE0h FFE0h FFE0h FFDFh 1 KB Flash FFDFh FFDFh FFDFh 4 KB 2 KB ROM Main Segment0,1 Flash FC00h F800h 4 KB Memory Segment0–7 ROM F000h F000h 10FFh 128B Flash 10FFh SegmentA 2 × 128B 1080h Information Flash Memory SegmentA,B 1000h 0FFFh 1 KB 1 KB Boot ROM Boot ROM 0C00
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 boot ROM containing bootstrap loader (continued) features of the bootstrap loader are: UART communication protocol, fixed to 9600 baud Port pin P1.1 for transmit, P2.2 for receive TI standard serial protocol definition Implemented in flash memory version only Program execution starts with the user vector at 0FFFEh or with the bootstrap loader (start vector is at address 0C00h) hardware resources used
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 boot ROM containing bootstrap loader (continued) Program execution begins with the bootstrap vector at 0C00h (boot ROM) if a minimum of two positive edges have been applied to TEST while RST/NMI is low, and TEST is high when RST/NMI goes from low to high. The TEST signal is normally used internally to switch pins P1.4, P1.5, P1.6, and P1.7 between their application function and the JTAG function. If the second
Summary of the content on the page No. 12
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 flash memory 0FFFFh Segment0 w/ The flash memory consists of 512-byte segments 0FE00h Interrupt Vectors in the main memory and 128-byte segments in the 0FDFFh information memory. See device memory maps Segment1 0FC00h for specific device information. 0FBFFh Segment2 Segment0 to Segment7 can be erased 0FA00h individually, or altogether as a group. 0F9FFh Segment3 0F800h SegmentA and SegmentB can be erased 0F7FF
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 flash memory control register FCTL1 (continued) Read access is possible at any time without restrictions. The control bits of control register FCTL1 are: 15 8 7 0 FCTL1 SEG WRT res. res. res. MEras Erase res. 0128h WRT rw–0 rw–0 r0 r0 r0 rw–0 rw-0 r0 FCTL1 read: 096h FCTL1 write: 0A5h Erase 0128h, bit1, Erase a segment 0: No segment erase will be started. 1: Erase of one segment is enabled. The segment to be e
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 flash memory, timing generator, control register FCTL2 (continued) The flash timing generator is reset with PUC. It is also reset if the emergency exit bit EMEX is set. Control register FCTL2 may not be written to if the BUSY bit is set; otherwise, an access violation will occur (ACCVIFG=1). Read access is possible at any time without restrictions. SSEL1 SSEL0 Write ’1’ to PUC EMEX FN5.......... FN0 0 ACLK 1 M
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 flash memory control register FCTL3 (continued) BUSY 012Ch, bit0, The BUSY bit shows if an access to the flash memory is allowed (BUSY=0), or if an access violation occurs. The BUSY bit is read-only, but a write operation is allowed. The BUSY bit should be tested before each write and erase cycle. The flash timing-generator hardware immediately sets the BUSY bit after start of a write, segment-write, erase, or
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 flash memory control register FCTL3 (continued) LOCK 012Ch, bit4, The lock bit may be set during any write, segment-erase, or mass-erase request. Any active sequence in progress is completed normally. In segment-write mode, the SEGWRT bit is reset and the WAIT bit is set after the mode ends. The lock bit is controlled by software or hardware. If an access violation occurs and the ACCVIFG is set, the LOCK bit i
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 ACCV ACCVIFG S FCTL1.1 ACCVIE Flash Module Flash Module IE1.5 Clear Flash Module PUC RST/NMI POR PUC KEYV VCC PUC System Reset Generator POR NMIFG S NMIRS IFG1.4 Clear NMIES TMSEL NMI WDTQn EQU PUC POR PUC NMIIE WDTIFG S IE1.4 IRQ Clear IFG1.0 Clear PUC WDT Counter OSCFault POR OFIFG S IFG1.1 IRQA TIMSEL OFIF WDTIE IE1.1 Clear IE1.0 Clear NMI_IRQA PUC PUC Watchdog Timer Module IRQA: Interrupt Request Accepted
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled easily with memory manipulation instructions. oscillator and system clock Three clocks are used in the system—the system (master) clock MCLK, the subsystem (master) clock SMCLK, and the auxiliary clock ACLK: Main system clock MCLK, used by the CPU and the system Subsystem clock SMCLK, used by the periph
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 oscillator and system clock (continued) DIVA 2 LFXT1CLK ACLK /1, /2, /4, /8 Auxiliary Clock O Off XTS SC XIN ACLKGEN SELM DIVM CPUOff LFXT1 OSCILLATOR 2 2 3 0,1 /1, /2, /4, /8, Off MCLK XOUT Main System Clock 2 MCLKGEN DCOCLK V V CC CC R SCG0 DCO MOD sel SELS DIVS SCG1 3 5 2 0 Digital Controlled Oscillator (DCO) 0 DC + /1, /2, /4, /8, Off SMCLK Generator Modulator (MOD) Subsystem Clock 1 1 P2.5/Rosc DCGEN DCOM
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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 digital I/O (continued) The seven registers are: • Input register 8 bits at port P1/P2 contains information at the pins • Output register 8 bits at port P1/P2 contains output information • Direction register 8 bits at port P1/P2 controls direction • Interrupt edge select 8 bits at port P1/P2 input signal change necessary for interrupt • Interrupt flags 8 bits at port P1/P2 indicates if interrupt(s) are pending
