Streszczenie treści zawartej na stronie nr. 1
Sundance Multiprocessor Technology Limited
Form : QCF42
Date : 6 July 2006
User Manual
Unit / Module Description: User Manual
Unit / Module Number: SMT348
Document Issue Number:
Issue Date:
Original Author: E.P
User Manual
Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside,
Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied nor
communicated to a third party without prior written permission.
© Sundance Multiprocessor
Streszczenie treści zawartej na stronie nr. 2
Revision History Issue Changes Made Date Initials 1.0.0 First release 06/11/06 E.P 1.0.1 Minor inconsistency about comports removed from 26/02/07 E.P block Diagram 1.0.2 Clarification about the elements in the JTAG chain 15/11/07 E.P 1.0.3 Updated JTAG header information. Wrong marking 29/02/08 E.P of position. Added chapters about bitstream formatting, FPGA configuration User Manual SMT348 Page 2 of 29 Last Edited: 29/02/2008 17:52:00
Streszczenie treści zawartej na stronie nr. 3
Table of Contents 1 Introduction ................................................................................................................ 6 2 Related Documents..................................................................................................... 7 2.1 Referenced Documents .............................................................................................7 2.2 Applicable Documents ................................................................................
Streszczenie treści zawartej na stronie nr. 4
7 Qualification Requirements ......................................................................................25 7.1 Qualification Tests..................................................................................................25 7.1.1 Meet Sundance standard specifications............................................................25 7.1.2 Speed qualification tests....................................................................................26 7.1.3 Integration qualificatio
Streszczenie treści zawartej na stronie nr. 5
Table of Figures Figure 1: Block Diagram ........................................................................................................9 Figure 2: CPLD state machine.............................................................................................13 Figure 3: FPGA connections to Bank1 of QDRII.................................................................14 Figure 4: Top View...............................................................................................
Streszczenie treści zawartej na stronie nr. 6
1 Introduction The SMT348 is an FPGA TIM module designed to be integrated in modular systems. It is designed to connect to the huge range of other TIM modules and carriers developed by Sundance. Sundance modular solutions provide flexible and upgradeable systems. The SMT348 is a TIM module aimed at completing the range of Sundance Virtex4 modules like SMT368, SMT362, SMT339. It provides a communications platform between an XC4VSX55 or XC4VLX160 FPGA and • 4 banks of QDR2 SRAM at a fre
Streszczenie treści zawartej na stronie nr. 7
2 Related Documents 2.1 Referenced Documents SUNDANCE SDB specification. SUNDANCE SHB specification SUNDANCE SLB specification Samsung QDRII Datasheet Spansion S29GLXXXN flash 2.2 Applicable Documents TI TIM specification & user’s guide. Samtec QSH Catalogue page Virtex 4 Datasheet User Manual SMT348 Last Edited: 29/02/2008 17:52:00
Streszczenie treści zawartej na stronie nr. 8
3 Acronyms, Abbreviations and Definitions 3.1 Acronyms and Abbreviations TIM Texas Instruments Module TI© DSP Texas Instrument Digital Signal Processor Xilinx© Xilinx© Field Programmable Gate Array. FPGA QDR Quad Data Rate CP ComPort. Communication interface SDB Sundance Digital Bus. Communication interface SHB Sundance High-Speed Bus. Communication interface 3.2 Definitions DSP Module Typically a TIM module hosting a TI DSP and, a Xilinx FPGA. FPGA-only Module A TIM with no
Streszczenie treści zawartej na stronie nr. 9
JTAG 4 Functional Description This module conforms to the TIM standard (Texas Instrument Module, See TI TIM specification & user’s guide) for single width modules. It sits on a carrier board. The carrier board provides power (5V, 3.3V, +/-12V), ground, communication links (Comport links) between all the modules fitted and a pathway to the host, for a non stand-alone system. The SMT348 requires a 3.3V power supply (as present on all Sundance TIM carrier boards), which must be provided
Streszczenie treści zawartej na stronie nr. 10
4.2 Module Description • Block1 and Block6 Xilinx Virtex 4 XC4VSX55/LX160 and configuration scheme. • Block2: QDR2 SRAM memory. • Block3: IO connectors for general purpose or dedicated interfaces. • Block4: 50MHz or 200MHz local clocks, and external clock input. • Block5: LEDs for development and in-use monitoring and general purpose use. 4.2.1 FPGA Xilinx Virtex 4 XC4VSX55FF1148 or XC4VLX160FF1148 FPGA. This device is packaged in a 1148-pin BGA package. 4.2.2 CPLD Xilinx Coolrunn
Streszczenie treści zawartej na stronie nr. 11
4.2.5 FPGA Configuration schemes Different schemes are available to provide maximum flexibility in systems where the SMT348 is involved: The FPGA configuration bitstream source is • On Comport 3: The CPLD is connected to the Comport 3 link of the SMT348 TIM connector. (See block1). A switch is used to select Comport 3 as the link that will be used to receive the bitstream. The CPLD allows for FPGA configuration in slave SelectMAP mode. • Using the on-board Flash memory. The CPLD monito
Streszczenie treści zawartej na stronie nr. 12
4.2.6 FPGA Reset Scheme The CPLD is connected to a TIM global Reset signal provided to the SMT348 via its primary TIM connector pin 30. (See TI TIM specification & User’s guide). This signal goes to the CPLD and the FPGA. Nevertheless as a general rule for good practice, the FPGA should not use this reset but should use the reset signal generated by the CPLD. The CPLD provides another signal called FPGAResetn that offers a better Reset control over the FPGA. At power up or on reception
Streszczenie treści zawartej na stronie nr. 13
Figure 2: CPLD state machine 4.2.7 FPGA Bitstream formatting If you generated you FPGA bitstream using Diamond FPGA, you do not need any other handling. The .app file created can be used as is to configure the FPGA. If you used Xilinx ISE and created a .bit file, you need to use the Sundance executable “Getrawdata.exe” provided for free in the SMT6001 package. Please read the SMT6001 help file at chapter: “Saving FPGA configuration data to file”. The
Streszczenie treści zawartej na stronie nr. 14
4.2.8 QDR2 SRAM Up to 4 Mbytes of QDR2 SRAM per bank. The memory is available as 4 independent banks. The QDR2 memory runs at 250MHz. Each bank is fully independent with separate address, control and data busses and arranged as follows: Figure 3: FPGA connections to Bank1 of QDRII The devices used are Samsung K7R321884M. Alternative part numbers, fully compatible can be fitted depending on availability at time of order. User Manual SMT348 Page 14 of 29 Last Edit
Streszczenie treści zawartej na stronie nr. 15
4.2.9 Sundance High speed Bus 2 x 60 pin connectors provide 80 IO connections between the FPGA and the outside word. They allow interfacing to other Sundance modules providing that you implement an SHB interface in the FPGA. (See 2.1) The SHB interface is available in Sundance SMT6500 support package. Either two 16-bit, or 1 32-bit interface can be implemented per connector. They allow interfacing to the outside world by implementing your own interface in the FPGA. The FPGA IO banks hosti
Streszczenie treści zawartej na stronie nr. 16
4.2.11 TIM Connectors TIM connectors provide 4 communication links (Comports) and a Global Bus to the FPGA. The comports which are available on the SMT348 are CP0, CP1, CP3, and CP4. They allow interfacing to Sundance TIM modules or to a Host PC providing that you implement a Comport Interface inside the FPGA. (See 2.1) The Comport interface is available in Sundance SMT6500 support package. The FPGA io banks hosting the Comport signals are powered using Vcco = 3.3v. The TIM connectors als
Streszczenie treści zawartej na stronie nr. 17
4.2.13 Clocking scheme The SMT348 module contains a 50MHz LVTTL clock, a 200MHz clock, and a connector for an external LVTTL clock input/output. 50 MHz LVTTL oscillator: Main system clock. Clocks the CPLD and the FPGA. Can be input in a DCM. 200MHz LVTTL oscillator: QDRII clock. Can also be used as a main FPGA clock. Can be input in a DCM. An external clock input is provided to the Virtex 4 FPGA via an MMCX connector. This connector is NOT fitted by default or if a mezzanine is require
Streszczenie treści zawartej na stronie nr. 18
As a result, check your main power supply ratings. If your system is likely to reach 25W per power rail we advice that you provide extra power to the carrier board using an external power supply. Name Quantity Voltage(V) Current(mA) Power(W) Source Device 3.3v power supply V33 1 3.3 7600 25 PCI specifications Table 4: Total available power. Nam Quantit Voltage(V) CurrenPower(W) Source Device e y t(mA) XC4VLX160FF1148-11 Vfpg1 1.2 1.805 2.166 Virtex-4 Vccint=1.2v a power (design im
Streszczenie treści zawartej na stronie nr. 19
Name Quantity Voltage Current(mA Power(W) Source Device (V) ) Samsung QDR II burst V18 4 1.8 800 5.76 Samsung QDRII (- 4 (18-bit interface) 25), datasheet rev1.1 p.9 ML6554CU DC/DC V18 1 1.8 0.01 0.018 Fairchild converter ML6554CU (obsolete) Coolrunner V18 1 1.8 0.55 0.00099 Ise 8.2.03i Xpower XC2C256CP132 software version: I.34 XC4VLX160FF1148-11 V18 1 1.8 829 1.497 Virtex-4 power HSTL II estimator (design implementation of 4 independent qdrii controllers) Total power consumed V
Streszczenie treści zawartej na stronie nr. 20
Name Quantity Voltage(V) Current(mA) Power(W) Source Device QDRII Vref VR09 8 0.9 0 0 Samsung QDRII (- 25), datasheet rev1.1 p.9 XC4VLX160FF1148-11 HSTL VR09 16 0.9 0.01 0.000144 DS302 (v1.17) Vref table 3 p.3 Total power consumed VR09 0.000144 HSTL Vref plane (0.9v) VR09 1 0.9 3 0.0027 Fairchild capacity ML6554CU (obsolete) Excess power 0.002556 Table 9: Power budget on QDRII and FPGA 0.9v reference voltage. Name Quantity Voltage(V) Current(mA) Power(W) Source Device 25 Mhz Cloc
