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CY7B9911V
3.3V RoboClock+™
High Speed Low Voltage Programmable Skew
Clock Buffer
Features Functional Description
■ All output pair skew <100 ps typical (250 max) The CY7B9911V 3.3V RoboClock+™ High Speed Low
Voltage Programmable Skew Clock Buffer (LVPSCB) offers
■ 3.75 to 110 MHz output operation
user selectable control over system clock functions. These
multiple output clock drivers provide the system integrator with
■ User selectable output functions
functions necessary to optimize the timing
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CY7B9911V 3.3V RoboClock+™ Pin Configuration PLCC 43 3 2 123130 5 29 2F0 3F1 4F0 6 28 GND 4F1 27 1F1 7 V 8 26 1F0 CCQ CY7B9911V V 9 25 V CCN CCN 4Q1 10 24 1Q0 4Q0 23 11 1Q1 GND 12 22 GND GND 13 21 GND 14 15 16 17 18 19 20 Pin Definitions Signal Name IO Description REF I Reference frequency input. This input supplies the frequency and timing against which all functional variations are measured. FB I PLL feedback input (typically connected to one of the eight outputs). FS I Three level frequency
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CY7B9911V 3.3V RoboClock+™ Skew Select Matrix Block Diagram Description The skew select matrix is comprised of four independent Phase Frequency Detector and Filter sections. Each section has two low skew, high fanout drivers (xQ0, xQ1), and two corresponding three level function select The Phase Frequency Detector and Filter blocks accept inputs (xF0, xF1) inputs. Table 2 shows the nine possible output from the Reference Frequency (REF) input and the Feedback functions for each section as determ
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CY7B9911V 3.3V RoboClock+™ [4] Figure 1 shows the typical outputs with FB connected to a zero skew output. Figure 1. The Typical Outputs with FB Connected to a Zero Skew Output FB Input REFInput 1Fx 3Fx 2Fx 4Fx (N/A) LM – 6t U LL LH – 4t U LM (N/A) – 3t U LH ML – 2t U ML (N/A) – 1t U MM MM 0t U MH (N/A) +1t U HL MH +2t U HM (N/A) +3t U HH HL +4t U (N/A) HM +6t U (N/A) LL/HH DIVIDED (N/A) HH INVERT If the TEST input is forced to its MID or HIGH state, the device Test Mode operates with its inter
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CY7B9911V 3.3V RoboClock+™ Operational Mode Descriptions Figure 2. Zero Skew and Zero Delay Clock Driver REF LOAD Z 0 L1 FB SYSTEM REF CLOCK FS LOAD 4Q0 4F0 L2 Z 4Q1 4F1 0 3Q0 3F0 3Q1 3F1 LOAD L3 2F0 2Q0 Z 0 2F1 2Q1 1F0 1Q0 L4 1F1 1Q1 LOAD TEST Z 0 LENGTH L1 = L2 = L3 = L4 Figure 2 shows the LVPSCB configured as a zero skew clock buffer. In this mode the CY7B9911V is used as the basis for a low skew clock distribution tree. When all the function select inputs (xF0, xF1) are left open, each of th
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CY7B9911V 3.3V RoboClock+™ groups, and the PLL aligns the rising edges of REF and FB, you Figure 5 shows the LVPSCB configured as a clock multiplier. The can create wider output skews by proper selection of the xFn 3Q0 output is programmed to divide by four and is sent back to inputs. For example, a +10 tU between REF and 3Qx is achieved FB. This causes the PLL to increase its frequency until the 3Q0 by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = and 3Q1 outputs are locked at 20 MHz,
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CY7B9911V 3.3V RoboClock+™ frequency, while still maintaining the low skew characteristics of and four or divide by two (and four) at the same time. This shifts the clock driver. The LVPSCB performs all of the functions its outputs over a wide range or maintain zero skew between described in this section at the same time. It can multiply by two selected outputs. Figure 7. Multi-Function Clock Driver REF LOAD Z 0 FB 110 MHz 27.5 MHz INVERTED REF DISTRIBUTION FS LOAD CLOCK 4Q0 4F0 27.5 MHz 4F1 4Q1
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CY7B9911V 3.3V RoboClock+™ Output Current into Outputs (LOW)............................. 64 mA Maximum Ratings Static Discharge Voltage........................................... > 2001V Operating outside these boundaries may affect the performance (MIL-STD-883, Method 3015) and life of the device. These user guidelines are not tested. Latch up Current..................................................... > 200 mA Storage Temperature ................................. –65°C to +150°C Operating Ra
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CY7B9911V 3.3V RoboClock+™ Capacitance [10] Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, V = 3.3V 10 pF IN A CC Note 10. Applies to REF and FB inputs only. AC Test Loads and Waveforms Figure 9. AC Test Loads and Waveforms V CC 3.0V 2.0V R1=100 2.0V R1 V =1.5V V =1.5V R2=100 th th 0.8V 0.8V C =30pF L C 0.0V (Includes fixture and probe capacitance) L R2 ≤1ns ≤1ns TT
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CY7B9911V 3.3V RoboClock+™ Switching Characteristics – 7 Option [2, 11] Over the Operating Range CY7B9911V-7 Parameter Description Unit Min Typ Max [1, 2] f Operating Clock FS = LOW 15 30 MHz NOM Frequency in MHz [1, 2] FS = MID 25 50 [1, 2 , 3] FS = HIGH 40 110 t REF Pulse Width HIGH 5.0 ns RPWH t REF Pulse Width LOW 5.0 ns RPWL t Programmable Skew Unit See Table 1 U [13, 14] t Zero Output Matched Pair Skew (XQ0, XQ1) 0.1 0.25 ns SKEWPR [13, 15] t Zero Output Skew (All Outputs) 0.3 0.75 ns SKE
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CY7B9911V 3.3V RoboClock+™ AC Timing Diagrams t t REF RPWL t RPWH REF t t ODCV PD t ODCV FB t JR Q t t SKEWPR, SKEWPR, t t SKEW0,1 SKEW0,1 OTHER Q t SKEW2 t SKEW2 INVERTED Q t SKEW3,4 t SKEW3,4 t SKEW3,4 REF DIVIDED BY 2 t t SKEW1,3, 4 SKEW2,4 REF DIVIDED BY 4 Document Number: 38-07408 Rev. *D Page 11 of 14 [+] Feedback
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CY7B9911V 3.3V RoboClock+™ Ordering Information Operating Accuracy (ps) Ordering Code Package Type Range 500 CY7B9911V-5JC 32-Pb Plastic Leaded Chip Carrier Commercial 500 CY7B9911V-5JCT 32-Pb Plastic Leaded Chip Carrier – Tape and Reel Commercial [23] 700 CY7B9911V-7JC 32-Pb Plastic Leaded Chip Carrier Commercial [23] 700 CY7B9911V-7JCT 32-Pb Plastic Leaded Chip Carrier – Tape and Reel Commercial Pb-Free 500 CY7B9911V-5JXC 32-Pb Plastic Leaded Chip Carrier Commercial 500 CY7B9911V-5JXCT 32-Pb P
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CY7B9911V 3.3V RoboClock+™ Package Diagram Figure 10. 32-Pin Plastic Leaded Chip Carrier J65 51-85002-*B Document Number: 38-07408 Rev. *D Page 13 of 14 [+] Feedback
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CY7B9911V 3.3V RoboClock+™ Document History Page Document Title: CY7B9911V 3.3V RoboClock+™ High Speed Low Voltage Programmable Skew Clock Buffer Document Number: 38-07408 Orig. of REV. ECN NO. Issue Date Description of Change Change ** 114350 3/20/02 DSG Change from Specification number: 38-00765 to 38-07408 *A 299713 See ECN RGL Added Tape and Reel and Pb-free Devices in the Ordering Information table Added 100 ps typical value for jitter (peak) *B 404630 See ECN RGL Minor Change: Added a no
