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ETM26E-03
Application Manual
Real Time Clock Module
RX-8801SA/JE
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NOTICE • The material is subject to change without notice. • Any part of this material may not be reproduced or duplicated in any form or any means without the written permission of Epson Toyocom. • The information, applied circuit, program, usage etc., written in this material is just for reference. Epson Toyocom does not assume any liability for the occurrence o
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RX - 8801 SA / JE Contents 1. Overview..........................................................................................................................1 2. Block Diagram .................................................................................................................1 3. Terminal description ........................................................................................................2 3.1. Terminal connections....................................
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RX − 8801 SA / JE 2 I C-Bus Interface Real-time Clock Module RX − 8801 SA / JE • Features built-in 32.768 kHz DTCXO, High Stability. 2 • Supports I C-Bus's high speed mode (400 kHz) • Alarm interrupt function for day, date, hour, and minute settings • Fixed-cycle timer interrupt function • Time update interrupt function (Seconds, minutes) • 32.768 kHz output with OE function (FOE and FOUT pins) • Auto correction of leap years (from 2000 to 2099) • Wide interface voltage r
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RX − 8801 SA / JE 3. Terminal description 3.1. Terminal connections RX − 8801 SA RX − 8801 JE 1./INT 20.N.C. 1. T1 (CE) 14. N.C. 2.GND 19.N.C. # 1 # 20 2.SCL 13.SDA 3. T2 (VPP) 18. N.C. 3.FOUT 12.T2 (VPP) 4.SDA 17.N.C. 5.N.C. 16.N.C. 4.N.C. 11.GND 6. T1 (CE) 15. N.C. 5.TEST 10./ INT 7.SCL 14.N.C. 8.FOUT 13.N.C. 6. VDD 9.N.C. # 10 # 11 9.N.C. 1 2.N.C. 7. FOE 8. N.C. 10. FOE 11. VDD SOP − 14pin VSOJ − 20pin 3.2. Pi
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RX − 8801 SA / JE 4. Absolute Maximum Ratings GND = 0 V Item Symbol Condition Rating Unit Supply voltage VDD Between VDD and GND −0.3 to +6.5 V Input voltage (1) VIN1 FOE pin GND−0.3 to VDD+0.3 V Input voltage (2) VIN2 SCL and SDA pins to +6.5 V GND−0.3 Output voltage (1) VOUT1 FOUT pin to VDD+0.3 V GND−0.3 Output voltage (2) VOUT2 SDA and /INT pins to +6.5 V GND−0.3 When stored separately, Storage temperature TSTG to +125 −55 °C without packaging 5. Recommended Operat
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RX − 8801 SA / JE 7. Electrical Characteristics 7.1. DC Characteristics *Unless otherwise specified, GND = 0 V, VDD = 1.6 V to 5.5 V, Ta = −40 °C to +85 °C Item Symbol Condition Min. Typ. Max. Unit Current fSCL = 0 Hz, / INT = VDD IDD1 1.2 3.4 VDD = 5 V consumption (1) FOE = GND μA Current FOUT : output OFF ( High Z ) IDD2 VDD = 3 V 0.8 2.1 consumption (2) Compensation interval 2.0 s Current fSCL = 0 Hz, / INT = VDD IDD3 3.0 7.5 VDD = 5 V consumption (3) FOE =
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RX − 8801 SA / JE * Unless otherwise specified, 7.2. AC Characteristics GND = 0 V , VDD = 1.8 V to 5.5 V , Ta = −40 °C to +85 °C Item Symbol Condition Min. Typ. Max. Unit SCL clock frequency fSCL 400 kHz Start condition setup time tSU;STA 0.6 μs Start condition hold time tHD;STA 0.6 μs Data setup time tSU;DAT 100 ns Data hold time tHD;DAT 0 900 ns Stop condition setup time tSU;STO 0.6 μs Bus idle time between tBUF 1.3 μs start condition and stop condition
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RX − 8801 SA / JE 8. Use Methods 8.1. Overview of Functions 1) Clock functions This function is used to set and read out month, day, hour, date, minute, second, and year (last two digits) data. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2099. 2) Fixed-cycle interrupt generation function The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed
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RX − 8801 SA / JE 8.2. Description of Registers 8.2.1. Register table Remark Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 SEC 40 20 10 8 4 2 1 ∗3 1 MIN 40 20 10 8 4 2 1 ∗3 2 HOUR 20 10 8 4 2 1 ∗3 3 WEEK 6 5 4 3 2 1 0 ∗3 4 DAY 20 10 8 4 2 1 ∗3 5 MONTH 10 8 4 2 1 ∗3 6 YEAR 80 40 20 10 8 4 2 1 − 7 RAM ∗4 • • • • • • • • − 8 MIN Alarm AE 40 20 10 8 4 2 1 ∗4 9 HOUR Alarm AE • 20 10 8 4 2 1 WEEK Alarm 6 5 4 3 2 1 0 A AE ∗4 DAY Alarm •
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RX − 8801 SA / JE 8.2.2. Control register (Reg F) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Control Register CSEL1 CSEL0 UIE TIE AIE RESET F (Default) (0) (1) (−) (−) (−) (0) (0) (−) ∗1) The default value is the value that is read (or is set internally) after powering up from 0 V. ∗2) "o" indicates write-protected bits. A zero is always read from these bits. ∗3) "−" indicates no default value has been defined. • This register is used to control interrup
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RX − 8801 SA / JE 3) AIE ( Alarm Interrupt Enable ) bit When an alarm timer interrupt event occurs (when the AF bit value changes from "0" to "1"), this bit's value specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an interrupt event is generated. When a "0" is written to this bit, no interr
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RX − 8801 SA / JE 8.2.3. Flag register (Reg-E) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Flag register UF TF AF VLF VDET E (Default) (0) (0) (0) (1) (1) (−) (−) (−) ∗1) The default value is the value that is read (or is set internally) after powering up from 0 V. ∗2) "o" indicates write-protected bits. A zero is always read from these bits. ∗3) "−" indicates a default value is undefined. • This register is used to detect the occurrence of various
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RX − 8801 SA / JE 8.2.4. Extension register (Reg-D) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Extension Register TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0 D (Default) (0) (0) (0) (−) (−) (−) (−) (−) ∗1) The default value is the value that is read (or is set internally) after powering up from 0 V. ∗2) "o" indicates write-protected bits. A zero is always read from these bits. ∗3) "−" indicates a default value is undefined. • This register is used to sp
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RX − 8801 SA / JE 8.2.5. RAM register (Reg - 7) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 7 RAM • • • • • • • • • This RAM register is read/write accessible for any data in the range from 00 h to FF h. 8.2.6. Clock counter (Reg - 0 ∼ 2) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 SEC 40 20 10 8 4 2 1 1 MIN 40 20 10 8 4 2 1 2 HOUR 20 10 8 4 2 1 ∗) "o" indicates write-protected bits. A zero is always read from these bits.
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RX − 8801 SA / JE 8.2.8. Calendar counter (Reg 4 to 6) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 DAY 20 10 8 4 2 1 5 MONTH 10 8 4 2 1 6 YEAR 80 40 20 10 8 4 2 1 ∗) "o" indicates write-protected bits. A zero is always read from these bits. • The auto calendar function updates all dates, months, and years from January 1, 2001 to December 31, 2099. • The data format is BCD format. For example, a date register value of "0011 0001" indicates the 31st
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RX − 8801 SA / JE 8.3. Fixed-cycle Timer Interrupt Function The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set between 244.14 μs and 4095 minutes. When an interrupt event is generated, the /INT pin goes to low level and "1" is set to the TF bit to report that an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin occurs only when the value of th
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RX − 8801 SA / JE 8.3.2. Related registers for function of time update interrupts. Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 B Timer Counter 0 128 64 32 16 8 4 2 1 C Timer Counter 1 • • • • 2048 1024 512 256 TEST WADA USEL FSEL1 FSEL0 D Extension Register TE TSEL1 TSEL0 UF AF VLF VDET E Flag Register TF CSEL1 CSEL0 UIE AIE RESET F Control Register TIE ∗1) "o" indicates write-protected bits. A zero is always read from these bits. ∗2) Bits marked wi
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RX − 8801 SA / JE 5) TIE (Timer Interrupt Enable) bit When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value specifies whether an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). TIE Data Description 1) When a fixed-cycle timer interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status remains Hi-Z). 2) When a fixed-cycle timer
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RX − 8801 SA / JE 8.4. Time Update Interrupt Function The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to the timing of the internal clock. When an interrupt event occurs, the UF bit value becomes "1" and the /INT pin goes to low level to indicate that an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the /INT pin occurs only when the value of the control
