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CY7C68000A
MoBL-USB™ TX2 USB 2.0 UTMI
Transceiver
■ Supports transmission of Resume Signaling
MoBL-USB™ TX2 Features
■ 3.3V Operation
■ UTMI-compliant and USB 2.0 certified for device operation
■ Two package options: 56-pin QFN and 56-pin VFBGA
■ Operates in both USB 2.0 High Speed (HS), 480 Mbits/second,
and Full Speed (FS), 12 Mbits/second
■ All required terminations, including 1.5 Kohm pull up on
DPLUS, are internal to chip
®
■ Optimized for Seamless Interface with Intel Monahans Appli-
c
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CY7C68000A An on-chip phase-locked loop (PLL) multiplies the 24 MHz oscil- Applications lator up to 30 or 60 MHz, as required by the transceiver parallel data bus. The default UTMI interface clock (CLK) frequency is Mobile Applications determined by the DataBus16_8 pin. ■ Smart Phones Buses ■ PDA Phones The two packages enable a 8- or 16-bit bidirectional data bus for ■ Gaming Phones data transfers to a controlling unit. ■ MP3 players Suspend and Tri-state Modes ■ Portable Media Players (PMP) Wh
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CY7C68000A Mode 0 enables the transceiver to operate with normal USB data Operational Modes decoding and encoding. The operational modes are controlled by the OpMode signals. Mode 1 enables the transceiver logic to support a soft disconnect The OpMode signals are capable of inhibiting normal operation feature that tri-states both the HS and FS transmitters, and of the transceiver and evoking special test modes. These modes removes any termination from the USB, making it appear to an take effect
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D4 28 V 43 CC D3 27 D14 44 V 26 D15 45 CC D2 25 Reserved 46 Reserved 24 Tri_state 47 D1 23 RXError 48 D0 22 RXActive 49 CLK 21 RXValid 50 DataBus16_8 20 GND 51 Uni_bidi 19 LineState1 52 GND 18 LineState0 53 TXValid 17 V 54 CC V 16 GND 55 CC ValidH 15 56 OpMode1 CY7C68000A Pin Configurations The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin VFBGA packages. The packages offered use either an 8-bit (60 MHz) or 16-bit (30 MHz) bus interface.
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CY7C68000A Figure 2. CY7C68000A 56-pin VFBGA Pin Assignment 12 345 678 1A 2A 3A 4A 5A 6A 7A 8A A 1B 2B 3B 4B 5B 6B 7B 8B B 1C 2C 3C 4C 5C 6C 7C 8C C 1D 2D 7D 8D D 1E 2E 7E 8E E F 1F 2F 3F 4F 5F 6F 7F 8F G 1G 2G 3G 4G 5G 6G 7G 8G H 1H 2H 3H 4H 5H 6H 7H 8H Document #: 38-08052 Rev. *G Page 5 of 15 [+] Feedback
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CY7C68000A Pin Descriptions Table 1. Pin Descriptions [1] QFN VFBGA Name Type Default Description 4H1 AVCC Power N/A Analog V This signal provides power to the analog section of the chip. CC 8H5 AVCC Power N/A Analog V This signal provides power to the analog section of the chip. CC 7H4 AGND Power N/A Analog Ground Connect to ground with as short a path as possible. 11 H8 AGND Power N/A Analog Ground Connect to ground with as short a path as possible. 9 H6 DPLUS I/O/Z Z USB DPLUS Signal Con
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CY7C68000A Table 1. Pin Descriptions (continued) [1] QFN VFBGA Name Type Default Description (continued) 24 B8 Tri_state Input Tri-state Mode Enable Places the CY7C68000A into Tri-state mode which tri-states all outputs and IOs. Tri-state Mode can only be enabled while suspended. 0: Disables Tri-state Mode 1: Enables Tri-state Mode 19 C2 LineState1 Output Line State These signals reflect the current state of the single-ended receivers. They are combinatorial until a “usable” CLK is available
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CY7C68000A Table 1. Pin Descriptions (continued) [1] QFN VFBGA Name Type Default Description (continued) 21 A4 RXValid Output Receive Data Valid This signal indicates that the DataOut bus has valid data. The Receive Data Holding Register is full and ready to be unloaded. The SIE is expected to latch the DataOut bus on the clock edge. 22 B7 RXActive Output Receive Active This signal indicates that the receive state machine has detected SYNC and is active. RXActive is negated after a bit stuf
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CY7C68000A Absolute Maximum Ratings Operating Conditions Storage Temperature ................................. –65°C to +150°C T (Ambient Temperature Under Bias) ............ 0°C to +70°C A Ambient Temperature with Power Supplied ..... 0°C to +70°C Supply Voltage ...............................................+3.0V to +3.6V Supply Voltage to Ground Potential ...............–0.5V to +4.0V Ground Voltage ................................................................. 0V DC Input Voltage to Any I
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CY7C68000A AC Electrical Characteristics USB 2.0 Transceiver USB 2.0-compliant in FS and HS modes. Timing Diagram HS/FS Interface Timing - 60 MHz Figure 3. 60 MHz Interface Timing Constraints CLK TCH_MIN TCSU_MIN Control_In TDH_MIN TDSU_MIN DataIn TCCO Control_Out TCDO DataOut Table 3. 60 MHz Interface Timing Constraints Parameters Parameter Description Min Typ Max Unit Notes T Minimum setup time for TXValid 4 ns CSU_MIN T Minimum hold time for TXValid 1 ns CH_MIN T Minimum setup time for Dat
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CY7C68000A HS/FS Interface Timing - 30 MHz Figure 4. 30 MHz Timing Interface Timing Constraints CLK TCH_MIN TCSU_MIN Control_In TDH_MIN TDSU_MIN DataIn TCDO TCCO TCVO Control_Out TVH_MIN TVSU_MIN DataOut Table 4. 30 MHz Timing Interface Timing Constraints Parameters Parameter Description Min Typ Max Unit Notes T Minimum setup time for TXValid 16 ns CSU_MIN T Minimum hold time for TXValid 1 ns CH_MIN T Minimum setup time for Data (Transmit direction) 16 ns DSU_MIN T Minimum hold time for Data
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CY7C68000A Ordering Information Ordering Code Package Type CY7C68000A-56LFXC 56 QFN CY7C68000A-56BAXC 56 VFBGA CY3683 MoBL-USB TX2 Development Board Package Diagrams The MoBL-USB TX2 is available in two packages: ■ 56-pin QFN ■ 56-pin VFBGA Figure 6. 56-Pin Quad Flatpack No Lead Package 8 x 8 mm (Sawn Version) LS56B 51-85187 *C Document #: 38-08052 Rev. *G Page 12 of 15 [+] Feedback
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CY7C68000A Package Diagrams (continued) Figure 7. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 TOP VIEW BOTTOM VIEW Ø0.05 M C Ø0.15 M C A B A1 CORNER PIN A1 CORNER Ø0.30±0.05(56X) 132648 5 6 85 7 6 41 3 2 A A B B C C D D E E F F G G H H 0.50 -B- 3.50 -A- 5.00±0.10 5.00±0.10 0.10(4X) SIDE VIEW REFERENCE JEDEC: MO-195C PACKAGE WEIGHT: 0.02 grams -C- SEATING PLANE 001-03901-*B ■ Connections between the USB connector shell and signal PCB Layout Recommendations ground must be done near the
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CY7C68000A For further information on this package design, refer to the appli- Quad Flat Package No Leads (QFN) Package cation note “Surface Mount Assembly of AMKOR’s MicroLead- Design Notes Frame (MLF) Technology.” Download this application note from AMKOR’s website, by following this link: Electrical contact of the part to the Printed Circuit Board (PCB) http://www.amkor.com/products/notes_papers/MLFApp is made by soldering the leads on the bottom surface of the Note.pdf. The application note
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CY7C68000A Document History Page Document Title: CY7C68000A MoBL-USB™ TX2 USB 2.0 UTMI Transceiver Document Number: 38-08052 Orig. of Submission REV. ECN NO. Description of Change Change Date ** 285592 KKU See ECN New data sheet *A 427959 TEH See ECN Addition of VFBGA Package information and Pinout, Removal of SSOP Package. Edited text and moved figure titles to the top per new template *B 470121 TEH See ECN Change from preliminary to final data sheet. Grammatical and formatting changes *C 47
