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TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Rev. 03 — 21 July 2000 Product specification
1. General description
The TDA8752B is a triple 8-bit ADC with controllable amplifiers and clamps for the
digitizing of large bandwidth RGB signals.
The clamp level, the gain and all other settings are controlled via a serial interface
2
(either I C-bus or 3-wire serial bus, selected via a logic input).
The IC also includes a PLL that can be locked to the horizontal line frequency and
gener
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps ■ Power-down mode 2 ■ Possibility to use up to four ICs in the same system when using the I C-bus interface, or more when using the 3-wire serial bus interface ■ 1.1 W power dissipation. 3. Applications ■ RGB high-speed digitizing ■ LCD panels drive ■ LCD projection systems ■ VGA and higher resolutions ■ Using two ICs in parallel, a higher display resolution can be obtained: 200 MHz pixel frequency. 4. Quick r
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps Table 1: Quick reference data…continued Symbol Parameter Conditions Min Typ Max Unit DR PLL divider ratio 100 - 4095 PLL P total power dissipation f = 110 MHz; ramp input - 1.1 - W tot clk j maximum PLL phase jitter f = 66.67 kHz; - 112 - ps PLL(rms) ref (RMS value) f = 110 MHz clk 5. Ordering information Table 2: Ordering information Type number Package Sampling frequency (MHz) Name Description Version TDA875
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps 6. Block diagram V V V V V V CLP AGND OGND AGND DGND CCA(R) CCA(B) CCO(R) CCO(B) CCA(PLL) SSD G G PLL V V V V V AGND AGND OGND OGND OGND CCA(G) DDD CCO(G) CCD CCO(PLL) R B R B PLL 11 19 27 40 79 69 59 95 99 85 89 13 21 29 41 70 60 48 96 82 86 9 6 RAGC RCLP 7 8 RGAINC RBOT 12 71 to 78 RIN CLAMP R0 to R7 10 RDEC MUX OUTPUTS ADC 45 3 ROR V ref RED CHANNEL 14 17 GAGC GCLP 16 15 GGAINC GBOT 61 to 68 20 GIN G0 to G7
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps CLP RAGC RCLP CLAMP CONTROL V P DAC 150 CLKADC kW RIN 8 AGC ADC REGISTER MUX ROR V ref 2 I C-bus: 8 bits (Or) 3 kW V 8 CCAR OUTPUTS R0 to R7 8 45 kW D OE DAC D ‡ R R 8 RBOT 5 1 7 REGISTER REGISTER 1 FINE GAIN ADJUST COARSE GAIN ADJUST 2 2 I C-bus: 5 bits (Fr) I C-bus: 7 bits (Cr) 2 I C-BUS FCE468 RGAINC HSYNCI Fig 2. Red channel diagram. 9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved. Prod
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps C C Z P COAST CKEXT INV CZ CP 2 I C-bus; 1 bit (Vlevel) loop filter 12 to 2 100 MHz I C-bus; CKREF 3 bits (Z) PHASE FREQUENCY VCO MUX 0°/180° CKADCO edge selector DETECTOR 2 I C-bus; 2 I C-bus; 1 bit phase selector A 2 I C-bus; 5 bits 2 bits (Vco) 2 (Edge) I C-bus; CLKADC (Ip, Up, Do) 2 I C-bus; 5 bits (Pa) 1 bit (Cka) MUX DIV N (100 to 4095) CKBO 2 2 I C-bus; 12 bits (Di) I C-bus; phase selector B 2 1 bit (C
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps 7. Pinning information 7.1 Pinning n.c. 1 80 CKREFO DEC2 2 79 V CCO(R) V 3 78 R7 ref DEC1 4 R6 77 n.c. 5 R5 76 RAGC 6 75 R4 RBOT 7 74 R3 RGAINC 8 73 R2 RCLP 9 72 R1 RDEC 10 71 R0 V 11 OGND 70 CCA(R) R RIN 12 V 69 CCO(G) AGND 13 G7 68 R GAGC 14 67 G6 GBOT 15 66 G5 TDA8752BH GGAINC 16 65 G4 GCLP 17 64 G3 GDEC 18 63 G2 V 19 G1 62 CCA(G) GIN 20 G0 61 AGND 21 60 OGND G G BAGC 22 59 V CCO(B) BBOT 23 58 B7 BGAINC 24
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps 7.2 Pin description Table 3: Pin description Symbol Pin Description n.c. 1 not connected DEC2 2 main regulator decoupling input 2 V 3 gain stabilizer voltage reference input ref DEC1 4 main regulator decoupling input 1 n.c. 5 not connected RAGC 6 red channel AGC output RBOT 7 red channel ladder decoupling input (BOT) RGAINC 8 red channel gain capacitor input RCLP 9 red channel gain clamp capacitor input RDEC 1
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps Table 3: Pin description…continued Symbol Pin Description 2 SDA 39 I C-bus/3-wire serial bus data input 2 V 40 logic I C-bus/3-wire serial bus digital power supply DDD 2 V 41 logic I C-bus/3-wire serial bus digital ground SSD 2 SCL 42 I C-bus/3-wire serial bus clock input n.c. 43 not connected n.c. 44 not connected ROR 45 red channel ADC output bit out of range GOR 46 green channel ADC output bit out of range
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps Table 3: Pin description…continued Symbol Pin Description CKREFO 80 reference output clock re-synchronized horizontal pulse CKAO 81 PLL clock output 3 (in phase with reference output clock CKAO or CKBO) OGND 82 PLL digital ground PLL CKBO 83 PLL clock output 2 CKADCO 84 PLL clock output 1 (in phase with internal ADC clock) V 85 PLL output power supply CCO(PLL) DGND 86 digital ground OE 87 output enable; active
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps 8. Functional description This triple high-speed 8-bit ADC is designed to convert RGB signals, coming from an analog source, into digital data used by a LCD driver (pixel clock up to 200 MHz when using 2 ICs). 8.1 IC analog video inputs The video inputs are internally DC polarized. These inputs are AC coupled externally. 8.2 Clamps Three independent parallel clamping circuits are used to clamp the video input
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps The calibration of the gains is done using the following principle. 1 From the reference voltage V a reference signal of 0.156 V (p-p) ( ⁄ V ) is ref 16 ref generated internally. During the synchronization part of the video line, the multiplexer, controlled by the TTL synchronization signal (HSYNCI, coming from HSYNC; see Figure 1) with a width equal to one of the video synchronization signals (e.g. the signal
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps ADC output code G NCOARSE 255 G G (max) (min) 227 coarse register value N COARSE (67 codes) 160 128 V N = 0 ref FINE N = 31 FINE FCE473 Fig 7. Fine gain correction for a coarse gain G . NCOARSE 8.4 ADCs The ADCs are 8-bit with a maximum clock frequency of 110 Msps. The ADCs input range is 1 V (p-p) full-scale. One out of range bit exists per channel (ROR, GOR and BOR). It will be at logic 1 when the signal is
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps Where: f = the natural PLL frequency n K = the VCO gain O DR = PLL divider ratio C and C = capacitors of the PLL filter. Z P The other PLL equation is as follows: f 1 1 n ⎛⎞ f = ----------------------------- - and ξ = -- - × ---- - (2) z ⎝⎠ 2π × R × C 2 f Z z Where: f = loop filter zero frequency z R = the chosen resistance for the filter ξ = the damping factor F = 0 dB loop gain frequency. O Different resistance
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps The PLL can be used in three different methods: The IC can be used as stand-alone with a sampling frequency of up to 110 MHz. • • When an RGB signal is at a pixel frequency exceeding 100 to 200 MHz, it is possible to follow one of the two possibilities given below: – Using one TDA8752B: the sampling rate can be reduced by a factor of two, by sampling the even pixels in the even frame and the odd pixels in the
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps COAST CKEXT INV 12 to 100 MHz MUX 0 /180 CKADCO phase selector A 2 I C-bus; 2 CLKADC I C-bus; 5 bits (Pa) 1 bit (Cka) (Cka = 1) CKBO MUX 2 CKREF I C-bus; PLL phase selector B 2 1 bit (Ckb) I C-bus; 5 bits (Pb) (Ckb = 1) NCKBO CKAO MUX Master TDA8752B 2 (even pixels) I C-bus; 1 bit (Ckab) (Ckab = 1) SYNCHRO CKREFO COAST CKEXT INV 12 to 100 MHz MUX 0 /180 CKADCO phase selector A 2 I C-bus; 2 CLKADC I C-bus; 5 bi
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps 2 9. I C-bus and 3-wire serial bus interfaces 9.1 Register definitions The configuration of the different registers is shown in Table 4. 2 Table 4: I C-bus and 3-wire serial bus registers Function Subaddress Bit definition Default name value A7 A6 A5 A4 A3 A2 A1 A0 MSB LSB SUBADDR-------- X X X Mode Sa3 Sa2 Sa1 Sa0 XXX1 0000 OFFSETR XXXX 0000Or7 Or6 Or5 Or4 Or3 Or2 Or1 Or0 0111 1111 COARSERXXXX 0001Or8 Cr6 Cr5 Cr
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps Table 5: Coding Programmed code Clamp code ADC output 0 - 63.5 underflow 1 - 63 2 - 62.5 ... ... 127 0 0 ... ... ... 254 63.5 63 or 64 255 64 64 256 120 120 ... ... ... 287 136 136 The default programmed value is: Programmed code = 127 • • Clamp code = 0 ADC output = 0. • 9.1.2 Coarse and fine registers These two registers enable the gain control, the AGC gain with the coarse register and the reference voltage w
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps Table 7: Gain correspondence (FINE) N Gain V to be full-scale (V) FINE i 0 0.825 1.212 31 0.878 1.139 The default programmed value is: N =0. FINE 9.1.3 Control register 2 COAST and HSYNC signals can be inverted by setting the I C-bus control bits ‘Vlevel’ and ‘Hlevel’ respectively. When ‘Vlevel’ and ‘Hlevel’ are set to zero respectively, COAST and HSYNC are active HIGH. The bit ‘Edge’ defines the rising or fall
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TDA8752B Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps Table 9: VCO register bits Z2 Z1 Z0 Resistance (kΩ) 0 0 0 high impedance 001128 01032 01116 1008 1014 1102 1111 Table 10: VCO gain control Vco1 Vco0 VCO gain (MHz/V) Pixel clock frequency range (MHz) 0 0 15 10to20 0 1 20 20to40 1 0 35 40to70 1150 70to110 The bits Vco1 and Vco0 control the VCO gain. The default programmed value is as follows: • Internal resistance = 16 kΩ VCO gain = 15 MHz/V. • 9397 750 07338 ©
