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AT91EB42
Evaluation Board
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User Guide
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Table of Contents Section 1 Overview............................................................................................... 1-1 1.1 Scope........................................................................................................1-1 1.2 Deliverables ..............................................................................................1-1 1.3 The AT91EB42 Evaluation Board .............................................................1-1 Section 2 Setting Up the AT91EB42
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Table of Contents Section 5 Appendix A – Configuration Straps....................................................... 5-1 5.1 Configuration Straps (CB1 - 23, JP1 - 8) ..................................................5-1 5.2 Power Consumption Measurement Strap (JP5) .......................................5-4 5.3 Ground Links (JP6) ...................................................................................5-4 5.4 Increasing Memory Size ......................................................
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Section 1 Overview 1.1 Scope The AT91EB42 Evaluation Board enables real-time code development and evaluation. It supports the AT91M42800. This guide focuses on the AT91EB42 Evaluation Board as an evaluation and demon- stration platform: Section 1 provides an overview. Section 2 describes how to set up the evaluation board. Section 3 details the on-board software. Section 4 contains a description of the circuit board. Section 5 and Section 6 are two appendices covering configuration
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Overview 2 x 32-pin EBI expansion connectors 2 x 32-pin I/O expansion connectors 20-pin JTAG interface connector If required, user-defined peripherals can also be added to the board. See Section 5 for details. Figure 1-1. AT91EB42 Evaluation Board Block Diagram AT91M42800 Reset Controller 8K Byte RAM SRAM ARM7TDMI Processor JTAG ICE EBI EBI Expansion Connector Connector ASB Flash 32.768 KHz Clock Crystal Generator AMBA Bridge Serial LEDs EEPROM Interrupt Push-buttons PIO Controller APB S
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Section 2 Setting Up the AT91EB42 Evaluation Board 2.1 Electrostatic The AT91EB42 Evaluation Board is shipped in protective anti-static packaging. The board must not be subjected to high electrostatic potentials. A grounding strap or similar Warning protective device should be worn when handling the board. Avoid touching the compo- nent pins or any other metallic element. 2.2 Requirements Requirements in order to set up the AT91EB42 Evaluation Board are: The AT91EB42 Evaluation Board itself
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Setting Up the AT91EB42 Evaluation Board 2.4 Jumper Settings JP1 is used to boot standard or user programs. For standard operations, set it in the STD position. JP8 is used to select the core power supply of the AT91M42800: 3.3V or 1.8V. For oper- ation at 1.8V, MCK frequency shall be limited to 17 MHz. For more information about jumpers and other straps, see Section 5. 2.5 Powering Up DC power is supplied to the board via the 2.1 mm socket (J1) shown in Figure 2-2. The polarity of the power sup
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Section 3 The On-board Software 3.1 AT91EB42 The AT91EB42 Evaluation Board embeds an AT49BV1604 Flash memory device pro- grammed with default software. Only the lowest 8 x 8 KB sectors are used. The Evaluation Board remaining sectors are user definable, and can be programmed using one of the Flash downloader solutions offered in the AT91 library. When delivered, the Flash memory device contains: the boot program the functional test software the SRAM downloader the Angel Debug Monitor
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The On-board Software 3.3 Programmed Table 3-1 defines the mapping defined by the boot program. Default Memory Table 3-1. Memory Map Mapping Part Name Start Address End Address Size Device Flash U1 0x01000000 0x011FFFFF 2M Bytes AT49BV1604 U2-U3 0x02000000 0x02040000 256K Bytes SRAM The boot software program, FTS and SRAM downloader are in sectors 1 and 2 of the Flash device. Sectors 2 to 8 support the Angel Debug Monitor. Sector 24 at address 0x0110 0000 must be programmed with a boot sequ
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Section 4 Circuit Description 4.1 AT91M42800 Figure 6-1 on page 6-2 shows the AT91M42800. The footprint is for a 144-pin TQFP package. Processor Strap CB20 enables the user to choose between the standard ICE debug mode and the JTAG boundary scan mode of operation. The operating mode is defined by the state of the JTAGSEL input detected at reset. Jumper JP5 (see Figure 6-8 on page 6-9 in Section 6, “Appendix B – Schematics”) can be removed by the user to allow measurement of the current demand
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Circuit Description 4.3 Memories The schematic (Figure 6-3 on page 6-4 in Section 6, “Appendix B – Schematics”) shows one AT49BV1604 2 MB 16-bit Flash, one AT45DB321 4 MB serial DataFlash, one AT24C512 64 KB EEPROM, one AT25256 32 KB EEPROM and two 128K/512K x 8 SRAM devices. Note: The AT91EB42 is fitted with two 128K x 8 SRAM devices. A footprint is provided for the user to fit a multi-chip device memory that embeds Flash (1 MB) and SRAM (128 KB) in a single component in place of the Flash and
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Circuit Description of watchdog time-out as the pin NWDOVF of the AT91M42800 is connected to its input MR. The assertion of this reset signal will light up the red RESET LED (D10). By pressing the CLEAR RESET push button (S1), the LED can be turned off. Another supervisory circuit initializes separately the microcontroller-embedded JTAG/ICE interface when the 3.3V supply voltage drops below 3.0V. Note that this volt- age can be changed, depending on the board production series. These separated r
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Circuit Description 4-4 AT91EB42 Evaluation Board User Guide
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Section 5 Appendix A – Configuration Straps 5.1 Configuration By adding the I/O and EBI expansion connectors, users can connect their own peripher- als to the evaluation board. These peripherals may require more I/O lines than available Straps (CB1 - 23, while the board is in its default state. Extra I/O lines can be made available by disabling JP1 - 8) some of the on-board peripherals or features. This is done using the configuration straps detailed below. Some of these straps present a defaul
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Appendix A – Configuration Straps CB7 Standard Power Supply Supervisory Enabling (1) Closed Standard power supply is supervised by the ADC (U20) channel 2 via a resistor bridge. The ratio is set to 0.1485 so that the standard power supply can be supervised up to 15V. Open Standard power supply is not connected to the ADC (U20) channel 2. This authorizes users to connect the corresponding ADC channel to their own resources via the I/O expansion connector. CB6, CB8 ADC Channels 3 and 4 Enablin
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Appendix A – Configuration Straps CB15 Serial DataFlash Enabling (1) Closed AT91 NPCSA0 select signal is connected to the serial DataFlash memory. Open AT91 NPCSA0 select signal is not connected to the serial DataFlash memory. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. CB17 SPI EEPROM Enabling (1) Closed EEPROM communication enabled Open EEPROM communication disabled. This authorizes users to connect the corresponding PIO to
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Appendix A – Configuration Straps JP1 User or Standard Boot Selection 2-3 The first half part of the Flash memory is accessible at its base address. 1-2 The second half part of the Flash memory is accessible at its base address. This authorizes users to download their own application software in this part and to boot on it. JP2 Push Button Enabling Open SW1-4 inputs to the AT91 are valid. Closed SW1-4 inputs to the AT91 are not valid. This authorizes users to connect the corresponding PIO to
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Section 6 Appendix B – Schematics 6.1 Schematics The following schematics are appended: Figure 6-1. PCB Layout Figure 6-2. AT91EB42 Blocks Overview Figure 6-3. EBI Memories Figure 6-4. I/O and EBI Expansion Connectors Figure 6-5. Push Buttons, LEDs and Serial Interface Figure 6-6. AT91M42800 Figure 6-7. Reset and JTAG Interface Figure 6-8. Power Supply and Battery Charger Figure 6-9. Battery Type and Connection 2 Figure 6-10. SPI Memories, I C Memories and SPI ADC The pin con
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Appendix B – Schematics Figure 6-1. PCB Layout 6-2 AT91EB42 Evaluation Board User Guide
