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TMS320DM646x DMSoC
Ethernet Media Access Controller (EMAC)/
Management Data Input/Output (MDIO)
Module
User's Guide
Literature Number: SPRUEQ6
December 2007
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2 SPRUEQ6–December 2007 Submit Documentation Feedback
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Contents Preface.............................................................................................................................. 10 1 Introduction.............................................................................................................. 12 1.1 Purpose of the Peripheral ..................................................................................... 12 1.2 Features ..............................................................................................
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4.3 PHY Acknowledge Status Register (ALIVE) ................................................................ 73 4.4 PHY Link Status Register (LINK)............................................................................. 73 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ............................ 74 4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) .......................... 75 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERI
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5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) ....................................... 116 5.37 MAC Hash Address Register 1 (MACHASH1) ............................................................ 117 5.38 MAC Hash Address Register 2 (MACHASH2) ............................................................ 117 5.39 Back Off Test Register (BOFFTEST)....................................................................... 118 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) ........
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List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 13 2 Ethernet Configuration—MII Connections .............................................................................. 15 3 Ethernet Configuration—GMII Connections ............................................................................ 17 4 Ethernet Frame Format..............................................................................................
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53 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ................................................ 96 54 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)............................................... 97 55 Receive Interrupt Mask Set Register (RXINTMASKSET)............................................................. 98 56 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ...................................................... 99 57 MAC Interrupt Status (Unmasked) Re
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List of Tables 1 EMAC and MDIO Signals for MII Interface ............................................................................. 16 2 EMAC and MDIO Signals for GMII Interface ........................................................................... 17 3 Ethernet Frame Description............................................................................................... 19 4 Basic Descriptor Description...................................................................................
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48 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions...................................... 93 49 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions................................ 94 50 MAC Input Vector Register (MACINVECTOR) Field Descriptions................................................... 95 51 MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions ................................... 95 52 Receive Interrupt Status (Unmasked) Regi
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Preface SPRUEQ6–December 2007 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the TMS320DM646x Digital Media System-on-Chip. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers description for each module. Nota
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www.ti.com Related Documentation From Texas Instruments SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. SPRUEQ6–December 2007 Read This First 11 Submit Documentation Feedback
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User's Guide SPRUEQ6–December 2007 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in theTMS320DM646x Digital Media System-on-Chip. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outsi
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www.ti.com Introduction • No-chain mode truncates frame to first buffer for network analysis applications. • Emulation support. • Loopback mode. 1.3 Functional Block Diagram Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: • EMAC control module • EMAC module • MDIO module The EMAC control module is the main interface between the device core processor and the EMAC module and MDIO module. The EMAC control module contains the necessary components to allow the EMAC to ma
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www.ti.com Architecture The EMAC and MDIO interrupts are combined within the control module, so only the control module interrupt needs to be monitored by the application software or device driver. The EMAC control module combines the EMAC and MDIO interrupts and generates 4 separate interrupts to the ARM through the ARM interrupt controller. See Section 2.16.4 for details of interrupt multiplex logic of the EMAC control module. 1.4 Industry Standard(s) Compliance Statement The EMAC peripheral c
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www.ti.com Architecture 2.2 Memory Map The EMAC peripheral includes internal memory that is used to hold information about the Ethernet packets received and transmitted. This internal RAM is 2K × 32 bits in size. Data can be written to and read from the EMAC internal memory by either the EMAC or the CPU. It is used to store buffer descriptors that are 4-words (16-bytes) deep. This 8K local memory holds enough information to transfer up to 512 Ethernet packets without CPU intervention. The packet
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www.ti.com Architecture Table 1. EMAC and MDIO Signals for MII Interface Signal Type Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The MTXD and MTXEN signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHZ at 10 Mbps operation and 25 MHZ at 100 Mbps operation. MTXD[3-0] O Transmit data (MTXD). The transmit data pins are a collection of 4 data signals comprising 4 bits of da
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www.ti.com Architecture 2.3.2 Gigabit Media Independent Interface (GMII) Connections Figure 3 shows a device with integrated EMAC and MDIO interfaced via a GMII connection. This interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes. The GMII interface supports 10/100/1000 Mbps modes. Only full-duplex mode is available in 1000 Mbps mode. In 10/100 Mbps modes, the GMII interface acts like an MII interface and only the lower 4 bits of data are transferred for each of the data buses. The
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www.ti.com Architecture Table 2. EMAC and MDIO Signals for GMII Interface (continued) Signal Type Description MCRS I Carrier sense (MCRS). The MCRS pin is asserted by the PHY when the network is not idle in either transmit or receive. The pin is de-asserted when both transmit and receive are idle. This signal is not necessarily synchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation only. MRCLK I Receive clock (MRCLK). The receive clock is a continuous clock that provides the t
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www.ti.com Architecture 2.4 Ethernet Protocol Overview Ethernet provides an unreliable, connection-less service to a networking application. A brief overview of the Ethernet protocol is given in the following subsections. For in-depth information on the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method, which is the Ethernet’s multiple access protocol, see the IEEE 802.3 standard document. 2.4.1 Ethernet Frame Format All the Ethernet technologies use the same frame s
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www.ti.com Architecture 2.4.2 Ethernet’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a result, when an EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex mode. When operating in full-duplex mode, there is no contention for use of a shared medium, since there are exactly two
