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ML310 User
Guide
Virtex-II Pro Embedded
Development Platform
UG068 (v1.01) August 25, 2004
R
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R "Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc. The shadow X shown above is a trademark of Xilinx, Inc. ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX,
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ML310 User Guide UG068 (v1.01) August 25, 2004 The following table shows the revision history for this document.. Version Revision 08/15/04 1.0 Initial Xilinx release. 08/25/04 1.01 Added SysACE CFGADDR details. UG068 (v1.01) August 25, 2004 www.xilinx.com ML310 User Guide 1-800-255-7778
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ML310 User Guide www.xilinx.com UG068 (v1.01) August 25, 2004 1-800-255-7778
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Table of Contents Preface: About This Manual Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK Virtex-II Pro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Summary of Virtex-II Pro Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PowerPC™ 405 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Roc
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R PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ALi South Bridge Interface, M1535D+, U15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Parallel Port Interface, connector assembly P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Serial Port Interface, connector assembly P1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 USB, connector
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R Preface About This Manual This manual accompanies the ML310 Embedded Development System and contains information about the ML310 Hardware Platform and software tools. Manual Contents This manual contains the following chapters: • Chapter 1, “Introduction to Virtex-II Pro, ISE, and EDK,” provides an overview of the hardware and software features. • Chapter 2, “ML310 Embedded Development Platform,” provides an overview of the embedded development platform and details the components and featur
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R Chapter : Resource Description/URL Problem Solvers Interactive tools that allow you to troubleshoot your design issues http://support.xilinx.com/support/troubleshoot/psolvers.htm Tech Tips Latest news, design tips, and patch information for the Xilinx design environment http://www.support.xilinx.com/xlnx/xil_tt_home.jsp Conventions This document uses the following conventions. An example illustrates each convention. Typographical The following typographical conventions are used in this docume
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R Convention Meaning or Use Example IOB #1: Name = QOUT’ Vertical ellipsis IOB #2: Name = CLKIN’ . Repetitive material that has . . been omitted . . . Repetitive material that has allow block block_name Horizontal ellipsis . . . been omitted loc1 loc2 ... locn; Online Document The following conventions are used in this document: Convention Meaning or Use Example See the section “Additional Cross-reference link to a Resources” for details. location in the current file or Blue text in ano
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R Chapter : 10 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004
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R Chapter 1 Introduction to Virtex-II Pro, ISE, and EDK Virtex-II Pro The Virtex-II Pro Platform FPGA solution is the most technically sophisticated silicon and software product development in the history of the programmable logic industry. The goal was to revolutionize system architecture “from the ground up.” To achieve that objective, the best circuit engineers and system architects from IBM, Mindspeed, and Xilinx co- developed the world's most advanced Platform FPGA silicon product. Leadi
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R Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK Table 1-1: Virtex-II Pro Family Members Device 2VP2 2VP4 2VP7 2VP20 2VP30 2VP40 2VP50 2VP70 2VP100 2VP125 Logic Cells 3,168 6,768 11,088 20,880 30,816 43,632 53,136 74,448 99,216 125,136 PPC405 011222 2224 MGTs 4488812 16 20 20 24 BRAM 216 504 792 1,584 2,448 3,456 4,176 5,904 7,992 10,008 (Kbits) Xtreme 12 28 44 88 136 192 232 328 444 556 Multipliers PowerPC™ 405 Core • Embedded 300+ MHz Harvard architecture core • Low power consumption:
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R Virtex-II Pro • Four levels of selectable pre-emphasis • Five levels of output differential voltage • Per-channel internal loopback modes • 2.5V transceiver supply voltage Virtex-II FPGA Fabric Description of the Virtex-II Family fabric follows: • SelectRAM memory hierarchy ♦ Up to 10 Mb of True Dual-Port RAM in 18 Kb block SelectRAM resources ♦ Up to 1.7 Mb of distributed SelectRAM resources ♦ High-performance interfaces to external memory • Arithmetic functions ♦ Dedicated 18-bit x 18-bit mu
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R Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK - 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers - Bus LVDS I/O - HyperTransport™ (LDT) I/O with current driver buffers - Built-in DDR input and output registers ♦ Proprietary high-performance SelectLink technology for communications between Xilinx devices - High-bandwidth data path - Double Data Rate (DDR) link - Web-based HDL generation methodology • SRAM-based in-system configuration ♦ Fast SelectMAP™
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R Foundation ISE IP. ISE even includes technology called IP Builder, which allows you to capture your own IP and reuse it in other designs. ISE’s Architecture Wizards allow easy access to device features like the Digital Clock Manager and Multi-Gigabit I/O technology. ISE also includes a tool called PACE (Pinout Area Constraint Editor) which includes a front-end pin assignment editor, a design hierarchy browser, and an area constraint editor. By using PACE, designers are able to observe and
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R Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK Board Level Integration Xilinx understands the critical issues such as complex board layout, signal integrity, high- speed bus interface, high-performance I/O bandwidth, and electromagnetic interference for system level designers. To ease the system level designers’ challenge, ISE provides support to all Xilinx leading FPGA technologies: • System IO • XCITE • Digital clock management for system timing • EMI control management for electro
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R Chapter 2 ML310 Embedded Development Platform Overview The ML310 Embedded Development Platform offers designers a versatile Virtex-II Pro XC2VP30-FF896 based platform for rapid prototyping and system verification. In addition to the more than 30,000 logic cells, over 2,400 Kb of BRAM, dual PowerPC™ 405 processors and RocketIO transceivers available in the FPGA, the ML310 provides an onboard Ethernet MAC/PHY, DDR memory, multiple PCI bus slots, and standard PC I/O ports within an ATX form
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R Chapter 2: ML310 Embedded Development Platform Figure 2-1: ML310 Board 18 www.xilinx.com ML310 User Guide 1-800-255-7778 UG068 (v1.01) August 25, 2004
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R Overview Figure 2-2 shows a high-level block diagram of the ML310 and its peripherals. INTC PLB BRAM OPB2PLB CF System ACE Bridge 256 MB OPB PLB Bus Bus DDR DIMM PLB2OPB RS232 Bridge High-Speed PPC SMBus 405 PM1 OCM Bus SPI OCM BRAM High-Speed XC2VP30 PM2 GPIO / LEDs FF896 PCI Bridge 3.3V PCI AMD RS232 Intel GD82559 TI Flash (2) RJ45 10/100 Ethernet NIC PCI 2250 3.3V PCI PS/2 GPIO ALi 5V PCI Slots K/M M1535D+ IDE Parallel South Bridge (2) Port 5V PCI USB SMBus Slots (2) Audio Figure 2-2: ML310
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R Chapter 2: ML310 Embedded Development Platform ♦ 2 USB ports ♦ 2 IDE connectors ♦ GPIO ♦ SMBus Interface ♦ AC97 Audio CODEC ♦ PS/2 keyboard and mouse ports • ATX power supply Board Hardware The ML310 Virtex-II Pro FPGA is connected to several peripherals listed below. The peripherals are either directly connected to the FPGA or in directly accessible via the PCI Bus. The following sections describe the main features of each of the peripherals and how they interface with the Xilinx Vi
