Intel 815 دليل المستخدم

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R







®
Intel 815 Chipset Platform
For Use with Universal Socket 370

Design Guide



April 2001












Document Number: 298349-001

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R ® Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relati

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R Contents 1 Introduction........................................................................................................................13 1.1 Terminology ..........................................................................................................14 1.2 Reference Documents ..........................................................................................16 1.3 System Overview ...........................................................................

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R 5.2 General Topology and Layout Guidelines.............................................................46 5.2.1 Motherboard Layout Rules for AGTL/AGTL+ Signals ...........................47 5.2.1.1 Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals .................................................................................49 5.2.1.2 THRMDP and THRMDN......................................................50 5.2.1.3 Additional Routing and Placement Considerations........

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R 7.3.2.2 AGP-Only Motherboard Guidelines......................................86 7.3.3 AGP Routing Guideline Considerations and Summary.........................87 7.3.4 AGP Clock Routing ...............................................................................88 7.3.5 AGP Signal Noise Decoupling Guidelines.............................................88 7.3.6 AGP Routing Ground Reference...........................................................89 7.4 AGP Down Routing Guideli

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R 10.2.5 Layout for Both Host-Side and Device-Side Cable Detection .............118 10.3 AC’97 ..................................................................................................................119 10.3.1 AC’97 Routing .....................................................................................119 10.3.2 AC’97 Signal Quality Requirements ....................................................121 10.3.3 Motherboard Implementation ...................................

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R 13.3.1 AGP Interface 1X Mode Checklist.......................................................158 13.3.2 Designs That Do Not Use the AGP Port .............................................159 13.3.3 System Memory Interface Checklist....................................................160 13.3.4 Hub Interface Checklist .......................................................................160 13.3.5 Digital Video Output Port Checklist ..................................................

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R Figures Figure 1. System Block Diagram .......................................................................................17 Figure 2. GMCH Block Diagram ........................................................................................18 Figure 3. Board Construction Example for 60 Ω Nominal Stackup ...................................25 Figure 4. GMCH 544-Ball µ BGA* CSP Quadrant Layout (Top View)................................27 Figure 5. ICH 241-Ball µ BGA* CSP Quadran

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R Figure 49. Schematic of RAMDAC Video Interface.........................................................102 Figure 50. Cross-Sectional View of a Four-Layer Board .................................................103 Figure 51. Recommended RAMDAC Component Placement & Routing........................104 Figure 52. Recommended RAMDAC Reference Resistor Placement and Connections 105 Figure 53. Hub Interface Signal Routing Example .........................................................

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R Tables Table 1. Processor Considerations for Universal Socket 370 Design...............................29 Table 2. GMCH Considerations for Universal Socket 370 Design ....................................30 Table 3. ICH Considerations for Universal Socket 370 Design.........................................30 Table 4. Clock Synthesizer Considerations for Universal Socket 370 Design ..................31 Table 5. Determining the Installed Processor via Hardware Mechanisms .............

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R Revision History Rev. No. Description Date -001 Initial Release. April 2001 ® Intel 815 Chipset Platform Design Guide 11

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R This page is intentionally left blank. ® 12 Intel 815 Chipset Platform Design Guide

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Introduction R 1 Introduction ® This design guide organizes Intel’s design recommendations for the Intel 815 chipset platform for use with the Universal Socket 370. In addition to providing motherboard design recommendations (e.g., layout and routing guidelines), this document also addresses system design issues (e.g., thermal requirements). This document contains design recommendations, board schematics, debug recommendations, and a system checklist. These design guidelines have

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Introduction R 1.1 Terminology This section describes some of the terms used in this document. Additional power delivery term definitions are provided at the beginning of Chapter 12, Power Delivery. Term Description Aggressor A network that transmits a coupled signal to another network is called the aggressor network. Aggressor A network that transmits a coupled signal to another network is called the aggressor network. AGP Accelerated Graphics Port AGTL/AGTL+ Refers to process

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Introduction R Term Description Ringback The voltage that a signal rings back to after achieving its maximum absolute value. Ringback may be due to reflections, driver oscillations, or other transmission line phenomena. Setup Window The time between the beginning of Setup to Clock (T ) and the arrival of a SU_MIN valid clock edge. This window may be different for each type of bus agent in the system. SSO Simultaneous Switching Output (SSO) Effects refers to the difference in elect

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Introduction R 1.2 Reference Documents Document Document Number / Location ® Intel 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for 298351 use with the Universal Socket 370 Datasheet ® Intel 82802AB/82802AC Firmware Hub (FWH) Datasheet 290658 ® Intel 82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub Datasheet 290655 ® Pentium II Processor Developer’s Manual 243341 ® Pentium III Processor Specification Update (latest revision from website) (http://develope

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Introduction R elimination of ISA provides true plug-and-play for the platform. Traditionally, the ISA interface was used for audio and modem devices. The addition of AC’97 allows the OEM to use software- configurable AC’97 audio and modem coder/decoders (codecs), instead of the traditional ISA devices. 1.3.1 System Features The Intel 815 chipset for use with the Universal Socket 370 platform contains two components: ® ® the Intel 82815 Graphics and Memory Controller Hub (GMCH) and

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Introduction R 1.3.2 Component Features Figure 2. GMCH Block Diagram System bus (66/100/133 MHz) Processor I/F SDRAM System 100/133 memory I/F MHz, 64 bit Primary display AGP I/F GPA Overlay RAMDAC Monitor Data or AGP stream Digital 2X/4X H/W cursor FP / TVout control & video out card Local memory I/F dispatch 3D pipeline 2D (blit engine) Internal graphics Hub I/F Hub comp_blk_1 1.3.2.1 Graphics Memory Controller Hub (GMCH) • Processor/System Bus Support ® ®  Opt

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Introduction R • Accelerated Graphics Port (AGP) Interface  Supports AGP 2.0, including 4X AGP data transfers, but not the 2X/4X Fast Write protocol  AGP universal connector support via dual-mode buffers to allow AGP 2.0 3.3V or 1.5V signaling  32-deep AGP request queue  AGP address translation mechanism with integrated fully associative 20-entry TLB  High-priority access support  Delayed transaction support for AGP reads that can not be serviced immediately  AGP semantic

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Introduction R ® 1.3.2.2 Intel 82801AA I/O Controller Hub (ICH) The I/O Controller Hub provides the I/O subsystem with access to the rest of the system, as follows: • Upstream accelerated hub architecture interface for access to the GMCH • PCI 2.2 interface (6 PCI Request/Grant pairs) • Bus master IDE controller; supports Ultra ATA/66 • USB controller • I/O APIC • SMBus controller • FWH interface • LPC interface • AC’97 2.1 interface • Integrated system management controller