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CY7C656xx
PRELIMINARY
EZ-USB HX2LP™
Low-Power USB 2.0 Hub Controller Family
1.0 Features 2.0 Introduction
• USB 2.0 hub controller EZ-USB HX2LP is Cypress’s next-generation family of high-
performance, low-power USB 2.0 hub controllers. HX2LP is an
Compliant with the USB 2.0 specification
ultra low-power single-chip USB 2.0 hub controller with
Windows Hardware-quality lab (WHQL)-compliant
integrated upstream and downstream transceivers, a USB
Serial Interface Engine (SIE), USB Hub Control
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PRELIMINARY CY7C656xx 3.0 Block Diagrams D+ D - High-Speed USB 2.0 PHY Serial USB Control Logic 24 Interface SPI_SCK MHz PLL SPI Comm unication Engine SPI_SD Crystal Block USB Upstream Port SPI_CS Transaction Translator (X4) Hub Repeater TT RAM Routing Logic USB Downstream Port 4 USB Downstream Port 1 USB Downstream Port 2 USB Downstream Port 3 USB 2.0 Port P ower Port USB 2.0 Port Power Port USB 2.0 Port Power Port USB 2.0 Port Power Port PHY Control Status PHY Control Status PHY Control Status
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PRELIMINARY CY7C656xx 3.0 Block Diagrams (continued) D+ D - High-Speed USB 2.0 PHY Serial USB Control Logic Interface 24 MHz SPI_SCK PLL SPI C om m unication Engine Crystal SPI_SD Block USB Upstream Port SPI_CS Transaction Translator (X1) Hub Repeater TT RAM Routing Logic USB Downstream Port 4 USB Dow nstream Port 1 USB Downstream Port 2 USB Dow nstream Port 3 USB 2.0 Port Power Port USB 2.0 Port Power Port USB 2.0 Port Power Port USB 2.0 Port Power Port PHY Control Status PHY Control Status PHY
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PRELIMINARY CY7C656xx 3.1 USB Serial Interface Engine (SIE) 5.0 Functional Overview The SIE allows the CY7C656xx to communicate with the USB The Cypress CY7C656xx USB 2.0 Hubs are a high-perfor- host through the USB repeater component of the HUB. The mance, low-system-cost solution for USB. The CY7C656xx SIE handles the following USB activity independently of the USB 2.0 Hubs integrate 1.5k upstream pull-up resistors for full- HUB Control Block: speed operation and all downstream 15k pull-down r
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PRELIMINARY CY7C656xx unpowered state. Once the hubs are configured, the ports are (Note that each port power output pin of the external power not driven, and the host may power the ports by sending a switch must be bypassed with an electrolytic or tantalum SetPortPower command to each port. After a port is powered, capacitor as required by the USB specification. These capac- any connect or disconnect event is detected by the hub. Any itors supply the inrush currents, which occur during change i
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PRELIMINARY CY7C656xx The LED control lines can also be modulated with a square Table 5-2 displays the color definition of the indicators when [1] wave for power conservation in systems using batteries. Alone CY7C656xx is in Manual Mode. with this there is also a polarity control for these pins, see section 9.3. Table 5-2. Port Indicator Color Definitions in Manual Mode In manual mode, the indicators are under the control of the Color Definition Port State host, which can turn on one of the L
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PRELIMINARY CY7C656xx 6.0 Pin Configuration 56 55 54 51 50 49 48 47 46 45 44 43 53 52 DD–[4]/NC 1 42 AMBER#[3]/NC DD+[4]/NC 2 41 GREEN#[3]/NC VCC 3 40 GND GND 4 39 VCC DD–[3]/NC 5 38 AMBER#[2] DD+[3]/NC 6 GREEN#[2] 37 VCC 7 36 AMBER#[1] GND 8 GREEN#[1] 35 DD–[2] GND 9 34 DD+[2] 10 33 VCC VCC 11 32 OVR#[2] GND 12 31 PWR#[2] DD–[1] 13 30 OVR#[1] DD+[1] 14 29 PWR#[1] 15 16 17 18 19 20 21 22 23 24 25 26 27 28 [2] Figure 6-1. 56-pin Quad Flat Pack No Leads (8 mm x 8 mm) Note: 2. NC are for CY7C65620
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PRELIMINARY CY7C656xx 7.0 Pin Description Table Table 7-1 below displays the pin assignments. [3] Table 7-1. Pin Assignments CY7C65640B / CY7C65620 CY7C65630 Pin Pin Name Type Default Description 3 3 VCC Power N/A V . This signal provides power to the chip. CC 7 7 VCC Power N/A V . This signal provides power to the chip. CC 11 11 VCC Power N/A V . This signal provides power to the chip. CC 15 15 VCC Power N/A V . This signal provides power to the chip. CC 19 19 VCC Power N/A V . This signal p
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PRELIMINARY CY7C656xx [3] Table 7-1. Pin Assignments (continued) CY7C65640B / CY7C65620 CY7C65630 Pin Pin Name Type Default Description Upstream Port 17 17 D– I/O/Z Z Upstream D– Signal. 18 18 D+ I/O/Z Z Upstream D+ Signal. Downstream Port 1 13 13 DD–[1] I/O/Z Z Downstream D– Signal. 14 14 DD+[1] I/O/Z Z Downstream D+ Signal. 36 36 AMBER#[1] O 1 LED. Driver output for Amber LED. Port Indicator Support. Default is Active LOW. Polarity is controlled through EEPROM. 35 35 GREEN#[1] O 1 LED. Driv
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PRELIMINARY CY7C656xx 8.0 Default Descriptors 8.1 Device Descriptor The standard device descriptor for CY7C656xx is based on the VID, PID, and DID found in the SPI EEPROM. This VID/PID/DID in the EEPROM will overwrite the default VID/PID/DID. If no EEPROM is used, the CY7C656xx will enumerate with the default descriptor values as shown below. Byte Full Speed High Speed Field Name Description 0 0x12 0x12 bLength 18 Bytes 1 0x01 0x01 bDescriptorType DEVICE_DESCRIPTOR 2,3 0x0110 0x0200 bcdUSB USB s
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PRELIMINARY CY7C656xx 8.4 Endpoint Descriptor Byte Full Speed High Speed Field Name Description 0 0x07 0x07 bLength 7 Bytes 1 0x05 0x05 bDescriptorType ENDPOINT_DESCRIPTOR 2 0x81 0x81 bEndpointAddress IN Endpoint #1 3 0x03 0x03 bmAttributes Interrupt 4,5 0x0001 0x0001 wMaxPacketSize Maximum Packet Size 6 0xFF 0x0C bInterval Polling Rate [9,10] 8.5 Interface Descriptor Byte Full Speed High Speed Field Name Description 0 N/A 0x09 bLength 9 Bytes 1 N/A 0x04 bDescriptorType INTERFACE_DESCRIPTOR 2 N
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PRELIMINARY CY7C656xx 8.8 Hub Descriptor Byte All Speed Field Name Description 0 0x09 bLength 9 Bytes 1 0x29 bDescriptorType HUB Descriptor [11] 20x04 bNbrPorts Number of ports supported, CY7C65640B or CY7C65630. 0x02 Number of ports supported, CY7C65620. [11] 3,4 0x0089 wHubCharacteristics b1, b0: Logical Power Switching Mode 00: Ganged power switching (all ports’ power at once) 01: Individual port power switching (Default in CY7C656xx) b2: Identifies a Compound Device, 0: Hub is not part of a
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PRELIMINARY CY7C656xx Byte 9: MaximumPower 9.2 Configured – 0xD2 Load This value is reported in the ConfigurationDescriptor:bMax- Byte Value (MSB->LSB) Power field and is the current in 2-mA intervals that is re- quired from the upstream hub. Default: 0x28 = 80 mA for 00xD2 full-speed and 0x57 = 174 mA for high-speed. 1 VID (LSB) Byte 10: HubControllerPower 2 VID (MSB) This value is reported in the HubDescriptor:bHubContrCur- 3 PID (LSB) rent field and is the current in milliamperes required by
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PRELIMINARY CY7C656xx Byte 4: PID (MSB)] Byte Value (MSB->LSB) Most Significant Byte of Product ID 7 EnableOverCurrentTimer[3:0], DisableOvercur- rentTimer[3:0] Byte 5: Reserved 8 MaxPower (Full-speed) Reserved. 9 MaxPower (High-speed) Byte 6: DID (MSB)] 10 Reserved Most Significant Byte of Device ID 11 Reserved Byte 7: EnableOvercurrentTimer[3:0], DisabledOvercur- rentTimer[3:0] 12 HubControllerPower Full-Speed Count time in ms for filtering overcurrent detection. Bits 7–4 13 HubControllerPow
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PRELIMINARY CY7C656xx tems that do not accept this, the IllegalHubDescriptor con- Bit 0: OverCurrentMode2—Reported as bit 3 of the wHub- figuration bit may be set to allow CY7C656xx to accept a Characteristics field of the hub descriptor. If Bit 1 of this byte DescriptorType of 0x00 for this command. Default is 0, rec- is set to ‘0’, over-current detection is enabled. If this bit (Bit ommended setting is 1. 0) is set to ‘1’, the hub reports over-current on a per-port basis. If set to ‘0’, the hu
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PRELIMINARY CY7C656xx Byte 22: ActivePorts[3:0] Byte c: iSerialNumber Bits 3–0 are the ActivePorts[3:0] bits that indicates if the Array of addresses for the iSerialNumber strings. Each ad- corresponding port is usable. For example, a two-port hub dress is two bytes long, stored LSB first. The array has that uses ports 1 and 4 would set this field to 0x09. The total NumLangs entries (2 * NumLangs bytes). number of ports reported in the Hub Descriptor: bNbrPorts The address c = b + 2 * NumLangs.
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PRELIMINARY CY7C656xx Table 10-1. Device Class Requests (continued) Request bmRequestType bRequest wValue wIndex wLength Data SetInterface 00000001B 0x0B Alternate Interface 0x0000 None Setting Number SetAddress 00000000B 0x05 Device Address 0x0000 0x0000 None SetDeviceRemoteWakeup 00000000B 0x03 0x01 0x0000 0x0000 None SetDeviceTest_J 00000000B 0x03 0x02 0x0100 0x0000 None SetDeviceTest_K 00000000B 0x03 0x02 0x0200 0x0000 None SetDeviceTest_SE0_NAK 00000000B 0x03 0x02 0x0300 0x0000 None SetDe
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PRELIMINARY CY7C656xx Table 10-2. Hub Class Requests (continued) Request bmRequestType bRequest wValue wIndex wLength Data ClearTTBuffer 00100011B 0x08 Dev_Addr, EP_Num TT_Port 0x0000 None ResetTT 00100000B 0x09 0x0000 Byte 0: 0x00 0x0000 None Byte 1: Port GetTTState 10100011B 0X0A TT_Flags Byte 0: 0x00 TT State TT State Byte 1: Port Length StopTT 00100011B 0x0B 0x0000 Byte 0: 0x00 0x0000 None Byte 1: Port Vendor Commands Read EEPROM 11000000B 0x02 0x00 0x00 Length Data This request results in
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PRELIMINARY CY7C656xx Upstream USB Connection 11.0 The following is a schematic of the USB upstream connector. BUSPOWER VCC D– D– 2.2 µ F 10V D+ D+ 100 kΩ GND SHELL 4.7 nF 250V 1 MΩ Figure 11-1. USB Upstream Port Connection Downstream USB Connections 12.0 The following is a schematic of the USB downstream connector. PWRx VCC 150 µF 0.01 µF DD–[X] D– 10V DD+[X] D+ GND SHELL Figure 12-1. USB Downstream Port Connection LED Connections 13.0 The following is a schematic of the LED circuitry. 3.3
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PRELIMINARY CY7C656xx 14.0 System Block Diagram 5V BUSPOWER VCC PWR1 VCC PWR1 DD–[1] D– PWR4 D– 2.2 µ F D– 150 µ F OVR1 DD+[1] 10V Power 10V D+ 0.01 µ F D+ PWR2 PWR3 D+ 100 kΩ Management GND OVR2 GND SHELL PWR2 PWR3 OVR3 SHELL PWR1 3.3V 4.7 nF 250V PWR4 680Ω GREEN#[1] OVR4 1 MΩ 680Ω AMBER#[1] SPI_SD SPI SPI_SCK PWR2 EEPROM VCC SPI_SD DD–[2] SPI_CS 150 µ F D– DD+[2] 10V D+ 0.01 µ F GND SHELL 24 MHz 3.3V 680Ω 3V GREEN#[2] 12 pF 12 pF 680Ω AMBER#[2] BUSPOWER BUSPOWER PWR3 VCC GREEN[1] GREEN[1] DD-[
