ページ1に含まれる内容の要旨
PRELIMINARY
DS80C390
Dual CAN High-Speed
Microprocessor
www.dalsemi.com
FEATURES PIN ASSIGNMENT
§ 80C52 compatible 48 33
- 8051 instruction-set compatible
- Four 8-bit I/O ports
49
32
- Three 16-bit timer/counters
- 256 bytes scratchpad RAM
§ High-Speed Architecture
DS80C390
- 4 clocks/machine cycle (8051=12)
- Runs DC to 40 MHz clock rates
- Frequency multiplier reduces EMI
17
- Single-cycle instruction in 100 ns
64
- 16/32-bit math coprocessor
§ 4 kB internal SRAM usable as
1 16
64-PIN QFP
pro
ページ2に含まれる内容の要旨
DS80C390 DESCRIPTION The DS80C390 is a fast 8051-compatible microprocessor. The redesigned processor core executes 8051 instructions up to 3 times faster than the original for the same crystal speed. The DS80C390 supports a maximum crystal speed of 40 MHz, resulting in apparent execution speeds of 100 MHz (approximately 2.5X). An optional internal frequency multiplier allows the microprocessor to operate at full speed with a reduced crystal frequency, reducing EMI. A hardware math accelerato
ページ3に含まれる内容の要旨
DS80C390 DS80C390 BLOCK DIAGRAM Figure 1 3 of 58 110199
ページ4に含まれる内容の要旨
DS80C390 PIN DESCRIPTION Table 1 LQFP PLCC SIGNAL DESCRIPTION NAME 8, 22, 17, 32, V +5V CC 40, 56 51, 68 9, 25, 1, 18, GND Digital Circuit Ground 41, 57 35, 52 46 57 ALE Address Latch Enable - Output. When the MUX pin is low, this pin outputs a clock to latch the external address LSB from the multiplexed address/data bus on Port 0. This signal is commonly connected to the latch enable of an external transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles
ページ5に含まれる内容の要旨
DS80C390 58-64, 2-8, 10 P1.0-P1.7 Port 1 - I/O. Port 1 can function as an 8-bit bi-directional I/O port, 1 the non-multiplexed A0 - A7 signals (when the MUX pin =1), and as an alternate interface for internal resources. Setting the SP1EC bit relocates RXD1 and TXD1 to Port 5. The reset condition of Port 1 is all bits at logic 1 via a weak pullup. The logic 1 state also serves as an input mode, since external circuits writing to the port can overdrive the weak pullup. When software clears any
ページ6に含まれる内容の要旨
DS80C390 13 22 P3.7 RD External Data Memory Read Strobe 34-27 45, 44, P4.0-P4.7 Port 4 - I/O. Port 4 can function as an 8-bit bi-directional I/O port, 42-37 and as the source for external address and chip enable signals for program and data memory. Port pins are configured as I/O or memory signals via the P4CNT register. The reset condition of Port 1 is all bits at logic 1 via a weak pullup. The logic 1 state also serves as an input mode, since external circuits writing to the port can overd
ページ7に含まれる内容の要旨
DS80C390 80C32 COMPATIBILITY The DS80C390 is a CMOS 80C32-compatible microcontroller designed for high performance. Every effort has been made to keep the core device familiar to 80C32 users while adding many new features. Because the device runs the standard 8051 instruction set, in general software written for existing 80C32- based systems will work on the DS80C390. The primary exceptions are related to timing-critical issues, since the high-performance core of the microcontroller executes i
ページ8に含まれる内容の要旨
DS80C390 required the same amount of time: two machine cycles or 24 oscillator cycles. In the DS80C390, the MOVX instruction takes as little as two machine cycles or 8 oscillator cycles but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are faster than their original counterparts, they now have different execution times. This is because the device usually uses one instruction cycle for each instruction byte. Examine the timing of each instruction for f
ページ9に含まれる内容の要旨
DS80C390 C0IR INTIN7 INTIN6 INTIN5 INTIN4 INTIN3 INTIN2 INTIN1 INTIN0 A5h C0TE A6h C0RE A7h IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 A8h SADDR0 A9h SADDR1 AAh C0M1C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP ABh C0M2C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP ACh C0M3C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP ADh C0M4C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP AEh C0M5C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP AFh P3 P3.7 P3.6 T1 T0 INT1 INT0 TXD0 RXD0 B0h C0M6C MSRDY ETI ERI INTRQ EXTRQ MTR
ページ10に含まれる内容の要旨
DS80C390 EIE CANBIE C0IE C1IE EWDI EX5 EX4 EX3 EX2 E8h MXAX EAh C1M1C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP EBh C1M2C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP ECh C1M3C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP EDh C1M4C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP EEh C1M5C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP EFh B F0h C1M6C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP F3h C1M7C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP F4h C1M8C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP F5
ページ11に含まれる内容の要旨
DS80C390 ARITHMETIC ACCELERATOR SEQUENCING Divide (32/16 or 16/16) Multiply (16x16) Load MA with dividend LSB. Load MB with multiplier LSB. Load MA with dividendLSB+1* Load MB with multiplier MSB. Load MA with dividend LSB+2* Load MA with multiplicand LSB. Load MA with dividend MSB. Load MA with multiplicand MSB. Load MB with divisor LSB. Poll the MST bit until cleared Load MB with divisor MSB. (6 machine cycles). Poll the MST bit until cleared Read MA for product MSB. (9 machine cycles). Read M
ページ12に含まれる内容の要旨
DS80C390 MEMORY ADDRESSING The DS80C390 incorporates three internal memory areas: § 256 bytes of scratchpad (or direct) RAM § 4 KB of SRAM configurable as various combinations of MOVX data memory, stack memory, and MOVC program memory § 512 bytes of RAM reserved for the CAN message centers. Up to 4 MB of external memory is addressed via a multiplexed or demultiplexed 20-bit address bus/8-bit data bus and four chip enable (active during program memory access) or four peripheral enable (active dur
ページ13に含まれる内容の要旨
DS80C390 INTERNAL MOVX SRAM The DS80C390 contains 4kB of SRAM that can be configured as user accessible MOVX memory, program memory, or optional stack memory. The specific configuration and locations are governed by the Internal Data Memory Configuration bits (IDM1, IDM0) in the Memory Control Register (MCON;C6h). Note that when the SA bit (ACON.2) is set, the first 1kB of the MOVX data memory is reserved for use by the 10-bit expanded stack. Internal memory accesses will not generate WR , RD ,
ページ14に含まれる内容の要旨
DS80C390 PROGRAM MEMORY CHIP ENABLE BOUNDARIES Table 7 P4CNT.5-3 CE0 CE1 CE2 CE3 000 0h-7FFFh 8000h-FFFFh 10000h-17FFFh 18000h-1FFFFh 100 0h-1FFFFh 20000h-3FFFFh 40000h-5FFFFh 60000h-7FFFFh 101 0h-3FFFFh 40000h-7FFFFh 80000h-BFFFFh C0000h-FFFFFh 110 0h-7FFFFh 80000h-FFFFFh 100000h-17FFFFh 180000h-1FFFFFh 111(default) 0-FFFFFh 100000h-1FFFFFh 200000h-2FFFFFh 300000h-3FFFFFh The DS80C390 incorporates a feature allowing PCE and CE signals to be combined. This is useful when incorporating modifiabl
ページ15に含まれる内容の要旨
DS80C390 The reset default of one Stretch cycle results in a three cycle MOVX for any external access. Therefore, the default off-chip RAM access is not at full speed. This is a convenience to existing designs that utilize slower RAM. When maximum speed is desired, software should select a Stretch value of zero. When using very slow RAM or peripherals, the application software can select a larger Stretch value. The specific timing of MOVX instructions as a function of Stretch settings is pro
ページ16に含まれる内容の要旨
DS80C390 ENHANCED DUAL DATA POINTERS The DS80C390 contains two data pointers, DPTR0 and DPTR1, designed to improve performance in applications that require high data throughput. Incorporating a second data pointer allows the software to greatly speed up block data (MOVX) moves by using one data pointer as a source register and the other as the destination register. DPTR0 is located at the same address as the original 8051 data pointer, allowing the DS80C390 to execute standard 8051 code with no
ページ17に含まれる内容の要旨
DS80C390 80C32 Idle and power down (Stop) modes, the DS80C390 provides a new Power Management Mode. This mode allows the processor to continue instruction execution, yet at a very low speed to significantly reduce power consumption (below even Idle mode). The DS80C390 also features several enhancements to Stop mode that make this extremely low power mode more useful. Each of these features is discussed in detail below. SYSTEM CLOCK CONTROL As mentioned previously, the microcontroller contains
ページ18に含まれる内容の要旨
DS80C390 SYSTEM CLOCK CONFIGURATION Table 10 CD1 CD0 Name Clocks/MC Max. External Frequency 4X/2X 0 0 0 Frequency Multiplier (2X) 2 20 MHz 0 0 1 Frequency Multiplier (4X) 1 10 MHz 0 1 N/A Reserved 1 0 N/A Divide-by-four (Default) 4 40 MHz 1 1 N/A Power Management Mode 1024 40 MHz The system clock and machine cycle rate changes one machine cycle after the instruction changing the control bits. Note that the change will affect all aspects of system operation, including timers and baud rates. Th
ページ19に含まれる内容の要旨
DS80C390 POWER MANAGEMENT MODE (PMM) Machine Cycle Rate Operating Current Estimates Full Operation PMM Full Operation PMM Crystal Speed (4 clocks per (1024 clocks per (4 clocks per (1024 clocks per machine cycle) machine cycle) machine cycle) machine cycle) 11.0592 MHz 2.765 MHz 10.8 kHz 13.1 ma 4.8 ma 16 MHz 4.0 MHz 15.6 kHz 17.2 ma 5.6 ma 25 MHz 6.25 MHz 24.4 kHz 25.7 ma 7.0 ma 33 MHz 8.25 MHz 32.2 kHz 32.8 ma 8.2 ma 40 MHz 10.0 MHz 39.1 kHz TBD TBD Note that power consumption in PMM is less t
ページ20に含まれる内容の要旨
DS80C390 Software should not rely on a lower-priority level interrupt source to remove PMM (Switchback) when a higher level is in service. Check the current priority service level before entering PMM. If the current service level locks out a desired Switchback source, then it would be advisable to wait until this condition clears before entering PMM. Alternately, software can prevent an undesired exit from PMM by intentionally entering a low priority interrupt service level before entering PM
