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YMF724F
Preliminary
DS-1
OVERVIEW
YMF724F (DS-1) is a high performance audio controller for the PCI Bus. DS-1 consists of two separated
functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block
allows Software Driver to handle maximum of 73 concurrent audio streams with the Bus Master DMA engine.
The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without
utilizing the CPU or causing system latency. By using
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YMF724F LOGOS GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI), and indicates GM system level 1 Compliant. XG logo is a trademark of YAMAHA Corporation. SONDIUS-XG logo is a trademark that Stanford University in the United States and YAMAHA Corporation hold jointly. Sensaura logo is a trademark of Central Research Laboratories Limited. 1. GM system level 1 GM system level 1 is a world standard format about MIDI synthesizer which pro
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YMF724F PIN CONFIGURATION YMF724F-V GP4 1 108 XRST# GP5 2 107 ACS# 106 GP6 3 ACDO 4 105 ACDI GP7 104 RXD 5 ASCLK 6 103 ASDO TXD 102 ROMDO/VOLDW# 7 ABCLK 8 101 ALRCK ROMSK/VOLUP# 100 VDD5 9 VSS VDD3 10 99 VSS VSS 11 98 VDD3 12 97 VDD5 VSS 96 IRQ5 13 PVDD 95 14 NC IRQ7 94 IRQ9 15 PCREQ# 93 16 PCGNT# IRQ10 92 IRQ11 17 SERIRQ# 91 INTA# 18 AD0 90 VSS 19 AD1 89 20 PVSS RST# 88 VDD5 21 AD2 87 22 AD3 PVSS 86 PCICLK 23 AD4 85 24 PVSS PVDD 84 GNT# 25 AD5 83 REQ# 26 AD6 82 AD31 27
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YMF724F PIN DESCRIPTION 1. PCI Bus Interface (53-pin) name I/O Type Size function PCICLK I P PCI Clock RST# I P Reset AD[31:0] IO Ptr Address / Data C/BE[3:0]# IO Ptr Command / Byte Enable PAR IO Ptr Parity FRAME# IO Pstr Frame IRDY# IO Pstr Initiator Ready TRDY# IO Pstr Target Ready STOP# IO Pstr Stop IDSEL I P ID Select DEVSEL# IO Pstr Device Select REQA# O P PCI Request GNTA# I P PCI Grant PCREQ# O Ptr PC/PCI Request PCGNT# I Ptr PC/PCI Grant PERR# IO Pstr Parity Err
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YMF724F 3. YMF727(AC3F2) Interface (9-pin) name I/O type size function XRST# O C 2mA Reset for local device ACS# O T 3mA Chip select for AC3F2 ASCLK O T 6mA Clock for Serial control data transfer of AC3F2 ACDO O T 3mA Serial control data output of AC3F2 ACDI I Tup - Serial control data input of AC3F2 ALRCK O T 3mA L/R clock for Serial audio data of AC3F2 ABCLK O T 6mA Bit clock for Serial audio data of AC3F2 ASDO O T 3mA Serial audio data output to AC3F2 ASDI I Tup - Mi
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YMF724F 6. Miscellaneous (15-pin) name I/O type Size function ROMCS O T 3mA Chip select for external EEPROM Serial clock for external EEPROM ROMSK / VOLUP# IO Tup 3mA or Hardware Volume (Up) Serial data output for external EEPROM ROMDO / VOLDW# IO Tup 3mA or Hardware Volume (Down) Serial data input for external EEPROM or Test pin ROMDI / TEST2# I Tup - (Do not connect externally when EEPROM is not.) XI24 I C - 24.576 MHz Crystal XO24 O C 2mA 24.576 MHz Crystal TEST[7:4,
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YMF724F BLOCK DIAGRAM PC-PCI / Legacy Audio D-DMA / S-IRQ AC-2 SB Pro Rate Converter Interface OPL3 / Mixer MPU401 Joystick SPDIF (output) PCI Bus BUS Master Interface PCI Audio DMA Controller XG Synthesizer AC3F2 Direct Sound Acc. Interface Wave In/Out Memory September 21, 1998 -7-
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YMF724F SYSTEM DIAGRAM September 21, 1998 -8- DirectX AC-3 DOS DLS MMSystem Application Application Appllication VM Win16API WaveOut MidiOut MidiIn WaveIn MidiOut Device Device Device Device Device Win32API DRV for Legacy DRV for PCI Audio Msjstck.drv XG/DLS DirectSound DirectSound I/O Traps I/O Traps Engine HAL VxD Soft DS-1 Slot Manager (Up to 64-sound) Effect VxD for Legacy VxD for PCI Audio Vjoyd.vxd PCI Audio Joystick OPL3 SB Pro MPU401 YMF724F(DS-1)
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YMF724F FUNCTION OVERVIEW 1. PCI INTERFACE DS-1 supports the PCI bus interface and complies to PCI revision 2.1. 1-1. PCI Bus Command DS-1 supports the following PCI Bus commands. 1-1-1. Target Device Mode C/BE[3:0]# Command 0000 Interrupt Acknowledge (not support) 0001 Special Cycle (not support) 0010 I/O Read 0011 I/O Write 0100 reserved 0101 reserved 0110 Memory Read 0111 Memory Write 1000 reserved 1001 reserved 1010 Configuration Read 1011 Configuration Write 1100 M
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YMF724F 1-2. PCI Configuration Register In addition to the Configuration Register defined by PCI Revision 2.1, DS-1 provides proprietary PCI Configuration Registers in order to control legacy audio function, such as OPL3, Sound Blaster Pro, MPU401 and Joystick. These additional registers are configured by BIOS or the configuration software from YAMAHA Corporation. The following shows the overview of the PCI Configuration Register. Offset b[31..24] b[23..16] b[15..8] b[
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YMF724F 00 - 01h: Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Vendor ID b[15:0] ........Vendor ID This register contains the YAMAHA Vendor ID registered in Revision 2.1. This register is hardwired to 1073h. 02 - 03h: Device ID Read Only Default: 000Dh Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Device ID b[15:0] ........Device ID This register contains
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YMF724F b8................SER: SERR# Enable This bit enables DS-1 to drive SERR#. “0”: Do not drive SERR#. (default) “1”: Drives SERR# when DS-1 detects an Address Parity Error on normal target cycle or a Data Parity Error on special cycle. 06 - 07h: Status Read / Write Clear Default: 0210h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DPE SSE RMA RTA STA DEVT DPD - - - CAP - - - - b4................CAP: Capability (Read Only) T
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YMF724F 08h: Revision ID Read Only Default: 03h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Revision ID b[7:0] ..........Revision ID This register contains the revision number of DS-1. This register is hardwired to 03h. 09h: Programming Interface Read Only Default: 00h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Programming Interface b[7:0] ..........Programming Interface This register indicates the programming interface of DS-1. This register
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YMF724F 0Dh: Latency Timer Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Latency Timer b[7:0] ..........Latency Timer When DS-1 becomes a Bus Master device, this register indicates the initial value of the Master Latency Timer. 0Eh: Header Type Read Only Default: 00h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Header Type b[7:0] ..........Header Type This register indicates the device type of DS-1. This is hardwired to 00
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YMF724F 2C-2Dh: Subsystem Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem Vendor ID b[15:0] ........Subsystem Vendor ID This register contains the Subsystem Vendor ID. In general, this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor. This register is read only. To write the IHV’s Vendor ID, use 44-45h (Subsystem Vendor ID Write
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YMF724F 3Ch: Interrupt Line Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Line b[7:0] ..........Interrupt Line This register indicates the interrupt channel that INTA# is assigned to. 3Dh: Interrupt Pin Read Only Default: 01h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Pin b[7:0] ..........Interrupt Pin DS-1 supports INTA# only. This register is hardwired to 01h. 3Eh: Minimum Grant Read Only Default: 0
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YMF724F 40 - 41h: Legacy Audio Control Read / Write Default: 907Fh Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 LAD SIEN MPUIRQ SBIRQ SDMA I/O MIEN MEN GPEN FMEN SBEN b0................SBEN: Sound Blaster Enable This bit enables the mapping of the Sound Blaster Pro block in the I/O space specified by the SBIO bits, when LAD is set to “0”. The OPL3 registers can be accessed via SB I/O space, while the SB block is enabled, even if
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YMF724F b[7:6] ..........SDMA: Sound Blaster DMA-8 Channel Select These bits select the DMA channel for the Sound Blaster Pro block. “0”: DMA ch0 “1”: DMA ch1 (default) “2”: reserved “3”: DMA ch3 b[10:8] ........SBIRQ: Sound Blaster IRQ Channel Select These bits select the interrupt channel for the Sound Blaster Pro block. “0”: IRQ5 (default) “1”: IRQ7 “2”: IRQ9 “3”: IRQ10 “4”: IRQ11 “5” - “7”: reserved. b[13:11] ......MPUIRQ: MPU401 IRQ Channel Select When MI
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YMF724F 42 - 43h: Extended Legacy Audio Control Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IMOD SBVER SMOD - - MAIM JSIO MPUIO SBIO FMIO b[1:0] ..........FMIO: FM I/O Address allocation These bits determine the base I/O address for the of the OPL3 block (FMBase). OPL3 block uses 4 bytes in the I/O address space. “0”: 388h (default) “1”: 398h “2”: 3A0h “3”: 3A8h b[3:2] ..........SBIO: SB I/O Addr
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YMF724F b[12:11] ......SMOD: SB DMA mode These bits determine the protocol to achieve the DMAC(8237) function on the PCI bus. “0”: PC/PCI (default) “1”: reserved “2”: Distributed DMA “3” reserved b[14:13] ......SBVER: SB Version Select These bits set the version of the SB Pro DSP. The value set in these bits is returned by sending the E1h DSP command. “0”: ver 3.01 (default) “1”: ver 2.01 “2”: ver 1.05 “3”: reserved b15..............IMOD: Legacy IRQ mode DS-1 s
