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TMS320DM643x DMP
DDR2 Memory Controller
User's Guide
Literature Number: SPRU986B
November 2007
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2 SPRU986B–November 2007 Submit Documentation Feedback
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Contents Preface ............................................................................................................................... 6 1 Introduction................................................................................................................ 7 1.1 Purpose of the Peripheral....................................................................................... 7 1.2 Features.............................................................................................
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List of Figures 1 Data Paths to DDR2 Memory Controller.................................................................................. 8 2 DDR2 Memory Controller Clock Block Diagram......................................................................... 9 3 DDR2 Memory Controller Signals........................................................................................ 11 4 Refresh Command ...................................................................................................
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List of Tables 1 PLLC2 Configuration....................................................................................................... 10 2 DDR2 Memory Controller Signal Descriptions ......................................................................... 11 3 DDR2 SDRAM Commands ............................................................................................... 12 4 Truth Table for DDR2 SDRAM Commands ............................................................................
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Preface SPRU986B–November 2007 Read This First About This Manual This document describes the DDR2 memory controller in the TMS320DM643x Digital Media Processor (DMP). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that r
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User's Guide SPRU986B–November 2007 DDR2 Memory Controller 1 Introduction This document describes the DDR2 memory controller in the TMS320DM643x Digital Media Processor (DMP). 1.1 Purpose of the Peripheral The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices. Memories types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The DDR2 memory controller is the major memory location for program and data storage. 1.2 Fe
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www.ti.com Introduction 1.3 Functional Block Diagram The DDR2 memory controller is the main interface to external DDR2 memory. Figure 1 displays the general data paths to on-chip peripherals and external DDR2 SDRAM. Master peripherals, EDMA, the ARM processor, and DSP can access the DDR2 memory controller through the switched central resource (SCR). Figure 1. Data Paths to DDR2 Memory Controller DSP Master DDR2 peripherals External memory SCR BUS BUS DDR2 SDRAM controller EDMA VPSS 1.4 Supported
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www.ti.com Peripheral Architecture 2 Peripheral Architecture This section describes the architecture of the DDR2 memory controller as well as how it is structured and how it works within the context of the system-on-a-chip. The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through programmable parameters such as the refresh rate, CAS latency, and man
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www.ti.com Peripheral Architecture 2.1.2 Clock Configuration The frequency of PLL2_SYSCLK1 is configured by selecting the appropriate PLL multiplier and divider ratio. The PLL multiplier and divider ratio are selected by programming registers within PLLC2. Table 1 shows a list of PLL multiplier and divider settings to achieve certain DDR2 frequencies. The data in Table 1 is derived by assuming a 27-MHZ reference clock. See the device-specific data manual for the clock frequencies that are suppor
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www.ti.com Peripheral Architecture 2.3 Signal Descriptions The DDR2 memory controller signals are shown in Figure 3 and described in Table 2. The following features are included: • The maximum data bus is 32-bits wide. • The address bus is 13-bits wide with an additional 3 bank address pins. • Two differential output clocks driven by internal clock sources. • Command signals: Row and column address strobe, write enable strobe, data strobe, and data mask. • One chip select signal and one clock en
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www.ti.com Peripheral Architecture 2.4 Protocol Description(s) The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 3. Table 4 shows the signal truth table for the DDR2 SDRAM commands. Table 3. DDR2 SDRAM Commands Command Function ACTV Activates the selected bank and row. DCAB Precharge all command. Deactivates (precharges) all banks. DEAC Precharge single command. Deactivates (precharges) a single bank. DESEL Device Deselect. EMRS Extended Mode Register set. Allows alteri
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www.ti.com Peripheral Architecture 2.4.1 Refresh Mode The DDR2 memory controller issues refresh commands to the DDR2 SDRAM memory (Figure 4). REFR is automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banks selected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at a rate defined by the refresh rate (RR) bit in the SDRAM refresh control register (SDRCR). Page information is always invalid before and after a REFR command;
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www.ti.com Peripheral Architecture 2.4.2 Deactivation (DCAB and DEAC) The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and mode set register commands (MRS and EMRS). During a DCAB command, DDR_A[10] is driven high to ensure the deactivation of all banks. Figure 5 shows the timing diagram for a DCAB command. Figure 5. DCAB Command DCAB DDR_CLK DDR_
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www.ti.com Peripheral Architecture The DEAC command closes a single bank of memory specified by the bank select signals. Figure 6 shows the timings diagram for a DEAC command. Figure 6. DEAC Command DEAC DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[12,11, 9:0] DDR_A[10] DDR_BA[2:0] DDR_DQM[3:0] SPRU986B–November 2007 DDR2 Memory Controller 15 Submit Documentation Feedback
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www.ti.com Peripheral Architecture 2.4.3 Activation (ACTV) The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of A[12:0] selects the row. When the DDR2 memory controller issues an ACTV command, a delay of t is incurred before RCD a read or write command is issued.
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www.ti.com Peripheral Architecture 2.4.4 READ Command Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READ command initiates a burst read operation to an active row. During the READ command, DDR_CAS drives low, DDR_WE and DDR_RAS remain high, the column address is driven on DDR_A[12:0], and the bank address is driven on DDR_BA[2:0]. The DDR2 memory controller uses a burst length of 8, and has a programmable CAS latency of 2, 3, 4, or 5. The CAS latency is t
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www.ti.com Peripheral Architecture 2.4.5 Write (WRT) Command Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the WRT command, a write latency is incurred. Write latency is equal to CAS latency minus 1. All writes have a burst length of 8. The use of the DDR_DQM outputs allows byte and halfword writes to be executed. Figure 9 shows the timing for a write on the DDR2 memory controller. If the transfer request is for less than 8 words, depending on the
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www.ti.com Peripheral Architecture 2.4.6 Mode Register Set (MRS and EMRS) DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable (on DDR2 device), single-ended strobe, etc. The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands. When the MRS or EMRS command is executed, the value on DDR_BA[1:0] selects
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www.ti.com Peripheral Architecture 2.5 Memory Width and Byte Alignment The DDR2 memory controller supports memory widths of 16 bits and 32 bits. Table 5 summarizes the addressable memory ranges on the DDR2 memory controller. See the device-specific data manual for the memory widths that are supported. Figure 11 shows the byte lanes used on the DDR2 memory controller. The external memory is always right-aligned on the data bus. Table 5. Addressable Memory Ranges Memory Width Maximum addressable b
