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GP4020 GPS Baseband Processor Design Manual
Publication Number: DM5280
Issue: 3
Revision: 002
Issued: January 2002
Zarlink Semiconductor, Cheney Manor
Swindon, Wiltshire, United Kingdom, SN2 2QW
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Manual Revision History Version Revision Date Update Summary 1 001 February 2000 First Version 2 001 August 2000 GND and VDD pins marked as type “PWR” in tables 2.2 and 20.1. Modified TESTMODE (pin 74) definition. TM ® Removal of extra " " and " " trade-markings throughout. New BSIO Introduction (Secs 6.1, 6.2) Extensive DMAC usage procedures added (Sec 8) and section 17.4 deleted. Updated MPC Configuration for Memory Area 3 (Sec 11) New Note 1 added in Section 14.6.2 Updated Address Map info in
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Contents Page Contents.........................................................................................................................................iii Related Products and Documents.................................................................................................... v Trademarks .................................................................................................................................... v Document References.......................................
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8.3 DMAC Triggering................................................................................................................ 99 8.4 Cautionary Notes.............................................................................................................. 101 9 GENERAL PURPOSE INPUT OUTPUT (GPIO) INTERFACE ....................................... 103 9.1 Introduction ...................................................................................................................... 10
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19.2 GP4020 Firefly MF1 Address Map..................................................................................... 183 20 INPUT / OUTPUT PIN CHARACTERISTICS .................................................................185 20.1 Pin Types ......................................................................................................................... 185 20.2 Input Delays .............................................................................................................
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Document References References to the following documents are made within the GP4020 GPS Baseband Processor Design Manual: 1) "ARM7TDMI Technical Reference Manual" ARM DDI 0029F, Rev 4 Copyright ARM Limited 2001. Arm Ltd. Documentation website (http://www.arm.com/arm/documentation?OpenDocument) Document Conventions The following terms which appear in the Manual, are defined here: a) External device: device such as a memory or logic; b) External Master: A Master device sited on the system bus
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1: Introduction 1 INTRODUCTION 1.1 GP4020 GPS Baseband Processor Overview This design manual describes the GP4020 GPS Baseband Processor, which is based on the Zarlink Semiconductor Firefly MF1 Microcontroller Core (ref. Firefly MF1 Core Design Manual (DM5003)), and a custom Navstar GPS C/A code 12-channel spread-spectrum correlator. The GP4020 is a complete digital baseband processor for a Global Positioning System (GPS) receiver. It combines TM the 12-channel correlator function of the GP202
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1: Introduction 1.3 Functional Description RTC_CLK REAL RTC_XIN GP4020 RTC_CMP_INT TIME CLOCK RTC_XOUT GPIO[7:0] WDOG GPIO NRESET PLL PLLAT1 PLLDT1 UART_CLK BSIO PERIPHERAL PR_XIN BSIO NPOR_RESET SYSTEM CONTROL TEST LOGIC CLOCK PR_XOUT POWER CONTROL LINES GENERATOR DISCOP CLK_I NRESET CK100KHz UART_INT DISCIO / CLK_T DISCIP1 UART_CLK BuILD_CLK M_CLK U2RXD NRESET NRESET UART2 SAMPCLK U2TXD 12 CHANNEL MAG0 DACK2 DREQ2 GPS BuILD_CLK NRESET CORRELATOR Firefly DMAC SIGN0 MF1 Core DACK DREQ U1RXD MEAS
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1: Introduction 1.3.1 ARM Processor (ARM7TDMI) The ARM7TDMI is a 32-bit RISC microprocessor core designed by Advanced RISC Machines (ARM). It uses a series 7 microprocessor Core, with the following functional extensions: • Thumb (16-bit) instruction set • Debug interface-using J-TAG. • Fast Multiplier • Embedded In-Circuit-Emulation capability The ARM7TDMI is object-code compatible with all earlier ARM6 and ARM7 based products. The ARM7TDMI is a fully static design and as such consumes dynamic
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1: Introduction Details can be found in section 6 "BµILD SERIAL INPUT OUTPUT (BSIO) INTERFACE" on page 33. 1.3.5 12 Channel Correlator (CORR) This module contains 12 channels of PRN code correlators for spread-spectrum correlation of 12 simultaneous signals. Each channel contains an independent carrier DCO to allow independent mix down of a satellite signal to base-band before code correlation occurs. The correlator is designed to extract data modulated at a nominal chipping-rate of 1.023MBPS, a
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1: Introduction 1.3.9 General Purpose Input Output (GPIO) This module provides eight I/O pins, which may be bit or byte addressed and configured in a latched or transparent mode. When in byte mode, buffer full/empty flags are available which can be used to generate an interrupt to the ARM7TDMI processor. Details can be found in section 9 "GENERAL PURPOSE INPUT OUTPUT (GPIO) INTERFACE" on page 103. 1.3.10 Interrupt Controller (INTC) The ARM7TDMI core accepts two types of interrupt: Normal (IRQ) a
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1: Introduction Since the internal SRAM is high-speed, it can be accessed with Zero wait-states through the Memory Peripheral Controller. Refer to section 11 "MEMORY PERIPHERAL CONTROLLER (MPC)" on page 109, for more information. 1.3.14 Real Time Clock (RTC) The GP4020 Real Time Clock uses an external 32kHz crystal to give an indication of time to the GP4020 chip, when the device is in Reset / Power Down. If a backup battery is included in a GPS receiver using the GP4020, the RTC will continue t
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1: Introduction Further details of the function and programming System Services Module can be found in Sections 2 and 8 of the "Firefly MF1 Core Design Manual" DM5003, available from Zarlink Semiconductor. 1.3.17 System Timer/Counters (SYSTIC) Two dual independent 32-bit timer/counters, with an 8-bit pre-scaler capability for each counter, are provided (Timers 1A, 1B, 2A and 2B). These are synchronous to the system clock and may be polled, or set-up to generate interrupts on over-run, with auto-
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1: Introduction 1.4 Typical Application M_CLK Figure 1.2 Block Diagram of typical GP4020 based GPS receiver 8 GP4020 GPS Baseband Processor Design Manual ANTENNA 10pF 10pF GP4020 +3.3V 32kHz Crystal 10M 22k STATIC RAM 1575MHz (72) (73) (84) (16-BIT) RF Main +3.3V FILTER RTC_ RTC_ SYSTEM ICE XIN XOUT SERVICES 22k 10k REAL TIME CLOCK ARM7TDMI TIMER / FLASH COUNTER (x2) 100k 100k BuILD 10nF EPROM _CLK (17) (58) FIREFLY MF1 (16-BIT) OPCLK+ CLK_T MICROCONTROLLER SYSTEM CLOCK 175MHz 10nF GENERATOR ME
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1: Introduction Figure 1.2 above shows a typical GPS receiver employing a GP2015 RF front–end, and a GP4020 correlator. The RF section, GP2015, performs down conversion of the L1 (1575.42MHz) signal for digital baseband processing. The resultant signal is then correlated in the GPS correlator within the GP4020 with an internally generated replica of the satellite PRN code to be received. Individual codes for each channel may be selected independently to enable acquisition and tracking of up to 1
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1: Introduction This page intentionally left blank. 10 GP4020 GPS Baseband Processor Design Manual
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2: GP4020 Package and Electrical Connections 2 GP4020 PACKAGE AND ELECTRICAL CONNECTIONS 2.1 GP4020 100-pin Package Dimensions The GP4020 GPS Baseband Processor is available from Zarlink Semiconductor in a 100-pin gull-wing Thin Quad Flat Package (TQFP). Ordering information for the GP4020 are shown in the “GP4020 GPS Baseband Processor Datasheet” DS5134, available from Zarlink Semiconductor. Figure 2.1 below shows the pin distribution around the package. Figure 2.2 on page 12 shows the default
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2: GP4020 Package and Electrical Connections Figure 2.2 GP4020 100-pin package outline drawing 12 GP4020 GPS Baseband Processor Design Manual
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2: GP4020 Package and Electrical Connections Symbol Dimensions in millimetres MIN Nominal MAX A 1.40 1.60 A1 0.05 0.15 A2 1.35 1.45 D 15.80 16.20 D1 13.80 14.20 D3 12.00 E 15.80 16.20 E1 13.80 14.20 E3 12.00 L 0.45 0.75 e 0.50 b 0.17 0.27 c 0.09 0.20 Table 2.1 GP4020 100-pin package dimensions 2.2 GP4020 100-pin Package Electrical Connection Details All Vdd and GND pins must be connected to ensure reliable operation. Any unused input pins must be tied either High or Low; no inputs should be lef
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2: GP4020 Package and Electrical Connections Pin Signal Name Type Circuit Description Notes No. Block 24 SDATA[7] I/O MPC System Data bit 7 1 25 NSOE I/O MPC System Output Enable - Active Low 1 26 NSWE[1] I/O MPC System Write Enable bit 1 - Active Low 1 27 NSWE[0] I/O MPC System Write Enable bit 0 - Active Low 1 28 SDATA[8] I/O MPC System Data bit 8 1 29 SDATA[9] I/O MPC System Data bit 9 1 30 VDD PWR 31 SDATA[10] I/O MPC System Data bit 10 1 32 SDATA[11] I/O MPC System Data bit 11 1 33 GND PWR
