Emerson PMPPC7448 دليل المستخدم

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User’s Manual
™
from Emerson Network Power
Embedded Computing
PmPPC7448: PowerPC™-Based Processor PMC Module September 2007

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The information in this manual has been checked and is believed to be accurate and reli- able. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER, EMBEDDED COMPUTING FOR ITS USE OR FOR ANY INACCURACIES. Specifications are sub- ject to change without notice. EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED HEREIN. This document does not convey any license under Emerson patents or the rights of others. Emers

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Regulatory Agency Warnings & Notices The Emerson PmPPC7448 meets the requirements set forth by the Federal Communica- tions Commission (FCC) in Title 47 of the Code of Federal Regulations. The following infor- mation is provided as required by this agency. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference

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Regulatory Agency Warnings & Notices (continued) EC Declaration of Conformity According to EN 45014:1998 Manufacturer’s Name: Emerson Network Power Embedded Computing Manufacturer’s Address: 8310 Excelsior Drive Madison, Wisconsin 53717 Declares that the following product, in accordance with the requirements of 2004/108/EEC, EMC Directive and 1999/5/EC, RTTE Directive and their amending directives, Product: PowerPC™-Based Processor PMC Module Model Name/Number: PmPPC7448/10005277-xx has been d

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Contents On-Card SDRAM . . . . . . . . . . . . . . . . . . . . .4-2 1Overview NVRAM Allocation . . . . . . . . . . . . . . . . . . .4-2 Components and Features . . . . . . . . . . . 1-1 Functional Overview . . . . . . . . . . . . . . . . 1-3 Physical Memory Map . . . . . . . . . . . . . . . 1-4 5System Controller Additional Information . . . . . . . . . . . . . . 1-6 CPU Interface . . . . . . . . . . . . . . . . . . . . . . .5-2 Product Certification . . . . . . . . . . . . . 1-6 CPU Interface R

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Contents (continued) Interrupt Pending Register (IPR) . . . 7-4 Power-up/Reset Sequence . . . . . . 11-2 Product ID Register (PIR). . . . . . . . . . . . . .7-5 POST Diagnostic Results . . . . . . . . 11-4 EReady Register (ERdy) . . . . . . . . . . . . . . .7-5 Monitor SDRAM Usage . . . . . . . . . . 11-4 Revision Registers . . . . . . . . . . . . . . . . . . .7-5 Monitor Recovery and Updates . . . . . . 11-4 Hardware Version Register (HVR) . . 7-6 Recovering the Monitor . . . . . . . . . 11-4 P

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Contents (continued) saveenv . . . . . . . . . . . . . . . . . . . . . .11-17 loop . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 setenv. . . . . . . . . . . . . . . . . . . . . . . .11-17 memmap . . . . . . . . . . . . . . . . . . . . 11-20 Test Commands . . . . . . . . . . . . . . . . . . 11-17 moninit . . . . . . . . . . . . . . . . . . . . . . 11-20 diags . . . . . . . . . . . . . . . . . . . . . . . . .11-18 pci. . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 mtest . . .

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Figures Figure 1-1: General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Figure 1-2: PmPPC7448 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Figure 2-1: Component Map, Top (Rev. 06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Figure 2-2: Component Map, Bottom (Rev. 06). . . . . . . . . . . . . . . . . . . . .

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Tables Table 1-1: Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Table 1-2: Regulatory Agency Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Table 1-3: Technical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Table 2-1: Circuit Board Dimensions . . . . . . . . . . . . . . . . .

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Registers Register 3-1: MPC7448 Hardware Implementation Dependent, HID0 . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Register 3-2: MPC7448 Hardware Implementation Dependent, HID1 . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Register 3-3: CPU Machine State Register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Register 3-4: L2 Cache Control Register (L2CR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Section 1 Overview The Emerson PmPPC7448 module is a Processor PCI Mezzanine Card (PPMC). It is based on the Freescale® Semiconductor PowerPC™ MPC7448 central processor unit and provides additional processing power for the baseboard, which must be compatible with PPMC architecture. The PmPPC7448 module supports various memory configurations, program- mable user Flash memory, a PCI bridge/controller, three Ethernet interfaces, two serial ports, as well as a real-time clock, and EEPROM. COMPON

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Overview: Components and Features Note: GbE ports (0 and 1) are routed through the PHYs directly to connector P14. Therefore, magnetics are required on the Rear Transition Module (RTM) or baseboard. CPLD: The PmPPC7448 uses a Complex Programmable Logic Device (CPLD) to implement various memory-mapped registers and to control access to the Flash, ROM socket, and enumera- tion of Monarch/non-Monarch systems. RTC: The real-time clock is an ST®Microelectronics M41T00 Serial Access Timekeeper®. Dev

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Overview: Functional Overview FUNCTIONAL OVERVIEW The following block diagram provides a functional overview for the PmPPC7448: Figure 1-1: General System Block Diagram   (;,   (;,                          21  ,45      95!:  768   %"#9: #$  $ %# 0 %#7)' ,<8   "&'( ) $ 

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Overview: Physical Memory Map PHYSICAL MEMORY MAP Fig. 1-1 illustrates the PmPPC7448 memory map: Figure 1-2: PmPPC7448 Memory Map  3     &-.6"!-  3" 3 # %"#-  3# -$5 5 * 6 -  3  23 -$5 3 0,-' 5 * 6 -  3' 23 5 * 6 -  3= -$5 %#0 -  3 3 5>0

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Overview: Physical Memory Map Table 1-1 summarizes the physical addresses for the PmPPC7448 and provides a reference to more detailed information: Table 1-1: Address Summary Hex Physical Access Address: Mode: Description: See Page: FF80,0000 R/W Boot Mirror – FF80,0000 R/W Boot Mirror – F854,0000 – Reserved – F850,0000 MV64460 SRAM 5-3 F830,0000 – Reserved – F820,E000 R/W PCI Reset Out Enable register 7-2 F820,D000 W DMC LED register 10-10 F820,C000 R Board Configuration register 3 (BCR3) 7-6

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Overview: Additional Information ADDITIONAL INFORMATION This section lists the PmPPC7448 hardware regulatory certifications and briefly discusses the terminology and notation conventions used in this manual. It also lists general technical references. Mean time between failures (MTBF) has been calculated at 309,632 hours using Telcordia Issue 1 Method I Case 3. Product Certification The PmPPC7448 hardware has been tested to comply with various safety, immunity, and emissions requirements as