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CY7C604XX
enCoRe™ V Low Voltage Microcontroller
Features
■ Powerful Harvard Architecture Processor ■ Programmable Pin Configurations
❐ M8C processor speeds running up to 24 MHz ❐ 25 mA sink current on all GPIO
❐ Low power at high processing speeds ❐ Pull Up, High Z, Open Drain, CMOS drive modes on all GPIO
❐ Interrupt controller ❐ Configurable inputs on all GPIO
❐ 1.71V to 3.6V operating voltage ❐ Low dropout voltage regulator for Port 1 pins. Programmable
to output 3.0, 2.5, or 1.8V at the I/
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CY7C604XX Functional Overview Getting Started The enCoRe V LV family of devices are designed to replace The quickest way to understanding the enCoRe V silicon is by multiple traditional low voltage microcontroller system compo- reading this data sheet and using the PSoC Designer Integrated nents with one, low cost single chip programmable component. Development Environment (IDE). This data sheet is an overview Communication peripherals (I2C/SPI), a fast CPU, Flash of the enCoRe V integrated circ
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CY7C604XX Development Tools ® PSoC Designer is a Microsoft Windows-based, integrated Assemblers. The assemblers allow assembly code to be development environment for the Programmable merged seamlessly with C code. Link libraries automatically use System-on-Chip (PSoC) devices. The PSoC Designer IDE runs absolute addressing or are compiled in relative mode, and linked on Windows XP or Windows Vista. with other software modules to get absolute addressing. This system provides design database mana
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CY7C604XX Designing with PSoC Designer The development process for the enCoRe V device differs from valuator functions. In the chip-level view, you perform the that of a traditional fixed function microprocessor. Powerful selection, configuration, and routing so that you have complete PSoC Designer tools get the core of your design up and running control over the use of all on-chip resources. in minutes instead of hours. Generate, Verify, and Debug The development process can be summarized in th
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CY7C604XX Document Conventions Acronyms Used Units of Measure The following table lists the acronyms that are used in this A units of measure table is located in the Electrical Specifications document. section. Table 7 on page 14 lists all the abbreviations used to measure the enCoRe V LV devices. Acronym Description Numeric Naming API application programming interface Hexadecimal numbers are represented with all letters in CPU central processing unit uppercase with an appended lowercase ‘h’ (fo
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CY7C604XX Pin Configuration 16-Pin Part Pinout Figure 1. CY7C60413 16-Pin enCoRe V LV Device Table 1. 16-Pin Part Pinout (QFN) Pin No. Type Name Description 1 I/O P2[5] Digital I/O, Crystal Out (Xout) 2 I/O P2[3] Digital I/O, Crystal In (Xin) 3 IOHR P1[7] Digital I/O, I2C SCL, SPI SS 4 IOHR P1[5] Digital I/O, I2C SDA, SPI MISO 5 IOHR P1[3] Digital I/O, SPI CLK 6 IOHR P1[1] Digital I/O, ISSP CLK, I2C SCL, SPI MOSI 7 Power Vss Ground Pin 8 IOHR P1[0] Digital I/O, ISSP DATA, I2C SDA, SPI CLK 9
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CY7C604XX 32-Pin Part Pinout Figure 2. CY7C60445 32-Pin enCoRe V LV Device P0[1] 1 24 P0[0] P2[7] 2 23 P2[6] P2[5] 3 22 P2[4] P2[3] 4 21 P2[2] QFN P2[1] 5 20 P2[0] (Top View) P3[3] 6 P3[2] 19 P3[1] 7 18 P3[0] P1[7] 8 17 XRES Table 2. 32-Pin Part Pinout (QFN) Pin No. Type Name Description 1 IOH P0[1] Digital I/O 2 I/O P2[7] Digital I/O 3 I/O P2[5] Digital I/O, Crystal Out (Xout) 4 I/O P2[3] Digital I/O, Crystal In (Xin) 5 I/O P2[1] Digital I/O 6 I/O P3[3] Digital I/O 7 I/O P3
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CY7C604XX Table 2. 32-Pin Part Pinout (QFN) (continued) Pin No. Type Name Description 17 Reset Input XRES Active high external reset with internal pull down 18 I/O P3[0] Digital I/O 19 I/O P3[2] Digital I/O 20 I/O P2[0] Digital I/O 21 I/O P2[2] Digital I/O 22 I/O P2[4] Digital I/O 23 I/O P2[6] Digital I/O 24 IOH P0[0] Digital I/O 25 IOH P0[2] Digital I/O 26 IOH P0[4] Digital I/O 27 IOH P0[6] Digital I/O 28 Power Vdd Supply voltage 29 IOH P0[7] Digital I/O 30 IOH P0[5] Digital I/O 31 IOH P0[3]
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CY7C604XX 48-Pin Part Pinout Figure 3. CY7C60455/CY7C60456 48-Pin enCoRe V LV Device 36 P2[6] NC 1 P2[7] 2 35 P2[4] P2[5] P2[2] 34 3 P2[3] 33 P2[0] 4 P2[1] 32 P4[2] 5 P4[3] 31 P4[0] 6 QFN P4[1] P3[6] 7 (Top View) 30 P3[7] P3[4] 29 8 P3[5] P3[2] 28 9 P3[3] P3[0] 27 10 XRES P3[1] 26 11 P1[6] 25 P1[7] 12 Table 3. 48-Pin Part Pinout (QFN) Pin No. Type Name Description 1NC NC No connection 2 I/O P2[7] Digital I/O 3 I/O P2[5] Digital I/O, Crystal Out (Xout) 4 I/O P2[3] Digital I/O, Crystal In (X
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CY7C604XX Table 3. 48-Pin Part Pinout (QFN) (continued) Pin No. Type Name Description 18 Power Vss Supply ground 19 NC NC No connection 20 NC NC No connection 21 Power Vdd Supply voltage (3, 4) 22 IOHR P1[0] Digital I/O, ISSP DATA, I2C SDA, SPI CLK 23 IOHR P1[2] Digital I/O 24 IOHR P1[4] Digital I/O, optional external clock input (EXTCLK) 25 IOHR P1[6] Digital I/O 26 XRES Ext Reset Active high external reset with internal pull down 27 I/O P3[0] Digital I/O 28 I/O P3[2] Digital I/O 29 I/O P3[4]
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CY7C604XX Register Reference The section discusses the registers of the enCoRe V LV device. It lists all the registers in mapping tables, in address order. Register Conventions Register Mapping Tables The register conventions specific to this section are listed in the The enCoRe V LV device has a total register address space of following table. 512 bytes. The register space is also referred to as IO space and is broken into two parts: Bank 0 (user space) and Bank 1 (config- Table 4. Register C
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CY7C604XX Table 5. Register Map Bank 0 Table: User Space Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access PRT0DR 00 RW 40 80 C0 PRT0IE 01 RW 41 81 C1 02 42 82 C2 03 43 83 C3 PRT1DR 04 RW 44 84 C4 PRT1IE 05 RW 45 85 C5 06 46 86 C6 07 47 87 C7 PRT2DR 08 RW 48 88 I2C_XCFG C8 RW PRT2IE 09 RW 49 89 I2C_XSTAT C9 R 0A 4A 8A I2C_ADDR CA RW 0B 4B 8B I2C_BP CB R PRT3DR 0C RW 4C 8C I2C_CP CC R PRT3IE 0D RW 4D 8D CPU_BP CD RW 0E 4E 8E CPU_CP CE R 0F 4F 8
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CY7C604XX Table 6. Register Map Bank 1 Table: Configuration Space Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access PRT0DM0 00 RW 40 80 C0 PRT0DM1 01 RW 41 81 C1 02 42 82 C2 03 43 83 C3 PRT1DM0 04 RW 44 84 C4 PRT1DM1 05 RW 45 85 C5 06 46 86 C6 07 47 87 C7 PRT2DM0 08 RW 48 88 C8 PRT2DM1 09 RW 49 89 C9 0A 4A 8A CA 0B 4B 8B CB PRT3DM0 0C RW 4C 8C CC PRT3DM1 0D RW 4D 8D CD 0E 4E 8E CE 0F 4F 8F CF PRT4DM0 10 RW 50 90 D0 PRT4DM1 11 RW 51 91 D1 12 52
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Valid Operating Region CY7C604XX Electrical Specifications This section presents the DC and AC electrical specifications of the enCoRe V LV devices. For the most up to date electrical specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com. Figure 4. Voltage versus CPU Frequency Figure 5. IMO Frequency Trim Options 3.6V 3.6V SLIMO SLIMO SLIMO Mode Mode Mode = 01 = 00 = 10 1.71V 1.71V 750 kHz 3 MHz 24 MHz 750 kHz 3 MHz
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CY7C604XX ADC Electrical Specifications Table 8. ADC Electrical Specifications Symbol Description Min Typ Max Units Conditions Input Input Voltage Range Vss 1.3 V This gives 72% of maximum code Input Capacitance 5 pF Resolution 8 Bits 8-Bit Sample Rate 23.4375 ksps Data Clock set to 6 MHz. Sample Rate = 0.001/(2^Resolution/Data clock) DC Accuracy DNL -1 +2 LSb For any configuration INL -2 +2 LSb For any configuration Offset Error 0 15 90
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CY7C604XX (6) Electro Static Discharge Voltage (ESD) .................. 2000V Maximum Ratings (7) Latch-up Current (LU) ........................................... 200 mA (5) o o o Storage Temperature (T ) -55 C to 125 C (Typical +25 C) STG Operating Conditions Supply Voltage Relative to Vss (Vdd)............. -0.5V to +4.0V DC Input Voltage (V )....................Vss - 0.5V to Vdd + 0.5V o o IO Ambient Temperature (T ).................................. 0 C to 70 C A DC Voltage Applied to Tri-
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CY7C604XX DC General Purpose I/O Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 1.71V to 3.6V and 0°C ≤ T ≤ 70°C. Typical parameters apply to 3.3V at 25°C. These are for design guidance only. A Table 10. 3.0V to 3.6V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units R Pull Up Resistor 4 5.6 8 k Ω PU V High Output Voltage IOH < 10 μA, maximum of 10 mA source Vdd - 0.2 – – V OH1 Port 2 or 3 Pins
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CY7C604XX Table 11. 2.4V to 3.0V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units R Pull Up Resistor 4 5.6 8 k Ω PU V High Output Voltage IOH < 10 μA, maximum of 10 mA source Vdd - 0.2 – – V OH1 Port 2 or 3 Pins current in all I/Os V High Output Voltage IOH = 0.2 mA, maximum of 10 mA source Vdd - 0.4 – – V OH2 Port 2 or 3 Pins current in all I/Os V High Output Voltage IOH < 10 μA, maximum of 10 mA source Vdd - 0.2 – – V OH3 Port 0 or 1 Pins with LDO Regulator current in a
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CY7C604XX Table 12. 1.71V to 2.4V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units R Pull Up Resistor 4 5.6 8 k Ω PU V High Output Voltage IOH = 10 μA, maximum of 10 mA Vdd - 0.2 – – V OH1 Port 2 or 3 Pins source current in all I/Os V High Output Voltage IOH = 0.5 mA, maximum of 10 mA Vdd - 0.5 – – V OH2 Port 2 or 3 Pins source current in all I/Os V High Output Voltage IOH = 100 μA, maximum of 10 mA Vdd - 0.2 – – V OH3 Port 0 or 1 Pins with LDO Regulator source current in
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CY7C604XX DC POR and LVD Specifications Table 13 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 13. DC POR and LVD Specifications Symbol Description Min Typ Max Units (9) Vdd Value for PPOR Trip V PORLEV[1:0] = 00b, HPOR = 0 1.61 1.66 1.71 V PPOR0 V PORLEV[1:0] = 00b, HPOR = 1 2.36 2.41 V PPOR1 V PORLEV[1:0] = 01b, HPOR = 1 2.60 2.66 V PPOR2 V PORLEV[1:0] = 10b, HPOR = 1 2.82 2.95 V PPOR3 Vdd Value for LVD Trip (10) V VM[2:0] = 000b 2.
