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SP601 Hardware
User Guide
[Guide Subtitle]
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UG5 UG518 ( 18 (v1. v1.1 1) ) A Au ugust gust 19, 19, 20 2009 [ 09 optional]
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any li
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Revision History The following table shows the revision history for this document. Date Version Revision 07/15/2009 1.0 Initial Xilinx release. 08/19/2009 1.1 • Added Appendix C, “VITA 57.1 FMC Connections.” • Updated Figure 1-18 and Figure 1-32. • Updated Table 1-4, Table 1-17, and Table 1-20. • Added introductory paragraph to Appendix D, “SP601 Master UCF.” • Miscellaneous typographical edits and new user guide template. UG518 (v1.1) August 19, 2009 www.xilinx.com SP601 Hardware User Guide
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SP601 Hardware User Guide www.xilinx.com UG518 (v1.1) August 19, 2009
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Table of Contents Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typographical. . . . . . . . . . .
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Appendix A: References Appendix B: Default Jumper and Switch Settings Appendix C: VITA 57.1 FMC Connections Appendix D: SP601 Master UCF 6 www.xilinx.com SP601 Hardware User Guide UG518 (v1.1) August 19, 2009
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Preface About This Guide This manual accompanies the Spartan®-6 FPGA SP601 Evaluation Board and contains information about the SP601 hardware and software tools. Guide Contents This manual contains the following chapters: • Chapter 1, “SP601 Evaluation Board,” provides an overview of the embedded development board and details the components and features of the SP601 board. • Appendix A, “References.” • Appendix B, “Default Jumper and Switch Settings.” • Appendix D, “SP601 Master UCF.” Addition
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Preface: About This Guide Convention Meaning or Use Example Variables in a syntax statement for which you must supply ngdbuild design_name values Italic font See the User Guide for more References to other manuals information. If a wire is drawn so that it Emphasis in text overlaps the pin of a symbol, the two nets are not connected. Items that are not supported or Dark Shading This feature is not supported reserved An optional entry or parameter. However, in bus specifications, ngdbuild
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Chapter 1 SP601 Evaluation Board Overview The SP601 board enables hardware and software developers to create or evaluate designs targeting the Spartan®-6 XC6SLX16-2CSG324 FPGA. The SP601 provides board features for evaluating the Spartan-6 family that are common to most entry-level development environments. Some commonly used features include a DDR2 memory controller, a parallel linear flash, a tri-mode Ethernet PHY, general- purpose I/O (GPIO), and a UART. Additional functionality can be add
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Chapter 1: SP601 Evaluation Board Features The SP601 board provides the following features: • 1. Spartan-6 XC6SLX16-2CSG324 FPGA • 2. 128 MB DDR2 Component Memory • 3. SPI x4 Flash • 4. Linear Flash BPI • 5. 10/100/1000 Tri-Speed Ethernet PHY • 7. IIC Bus ♦ 8Kb NV memory ♦ External access 2-pin header ♦ VITA 57.1 FMC-LPC connector • 8. Clock Generation ♦ Oscillator (Differential) ♦ Oscillator Socket (Single-Ended, 2.5V or 3.3V) • SMA Connectors (Differential) • 9. VITA 57.1 FMC-LPC Connector • 1
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Related Xilinx Documents Block Diagram Figure 1-1 shows a high-level block diagram of the SP601 and its peripherals. X-Ref Target - Figure 1-1 LEDs FMC LPC 10/100/1000 DIP Switch Expansion Connector Ethernet GMII GPIO Header USB DED JTAG Connector Bank 0 2.5 V Parallel Flash Spartan-6 DDR2 Bank 1 Bank 3 XC6SLX16 2.5V 1.8V Differential Clock U1 Clock Socket SMA Clock Pushbuttons Bank 2 2.5V IIC EEPROM MODE SPI x4 or USB UART and Header DIP Switch External Config UG518_01_070809 Figure 1-1: SP601
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Chapter 1: SP601 Evaluation Board Detailed Description Figure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and the section headings in this document. X-Ref Target - Figure 1-2 14 14 13 13 15 15 99 88 22 11 16 16 77 11 11 44 88 33 55 12 12 10 10 66 13 13 Figure 1-2: SP601 Board Photo The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1. Table 1-1: SP601 Features Schematic Number Feature Notes Page 1 Spartan-6 FPGA XC6SLX16-2CSG
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Detailed Description Table 1-1: SP601 Features (Cont’d) Schematic Number Feature Notes Page 9 VITA 57.1 FMC-LPC LVDS signals, clocks, PRSNT 6 connector 10 LEDs Ethernet PHY Status 7 11 LED, Header FPGA Awake LED, Suspend Header 8 12 LEDs FPGA INIT, DONE 9 LED User I/O (active-High) 9 DIP Switch User I/O (active-High) 9 13 Pushbutton User I/O, CPU_RESET (active-High) 9 12-pin (8 I/O) Header 6 pins x 2 male header with 8 I/Os 10 (active-High) 14 Pushbutton FPGA_PROG_B 9 15 USB JTAG Cypress USB to
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Chapter 1: SP601 Evaluation Board Table 1-2: I/O Voltage Rail of FPGA Banks (Cont’d) FPGA Bank I/O Voltage Rail 22.5V 31.8V References See the Xilinx Spartan-6 FPGA documentation for more information at http://www.xilinx.com/support/documentation/spartan-6.htm. 2. 128 MB DDR2 Component Memory There are 128 MB of DDR2 memory available on the SP601 board. A 1-Gb Elpida EDE1116ACBG (84-ball) DDR2 memory component is accessible through Bank 3 of the LX16 device. The Spartan-6 FPGA hard memory co
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Detailed Description Table 1-5 shows the connections and pin numbers for the DDR2 Component Memory. Table 1-5: DDR2 Component Memory Connections Memory U2 FPGA U1 Schematic Netname Pin Number Name J7 DDR2_A0 M8 A0 J6 DDR2_A1 M3 A1 H5 DDR2_A2 M7 A2 L7 DDR2_A3 N2 A3 F3 DDR2_A4 N8 A4 H4 DDR2_A5 N3 A5 H3 DDR2_A6 N7 A6 H6 DDR2_A7 P2 A7 D2 DDR2_A8 P8 A8 D1 DDR2_A9 P3 A9 F4 DDR2_A10 M2 A10 D3 DDR2_A11 P7 A11 G6 DDR2_A12 R2 A12 L2 DDR2_DQ0 G8 DQ0 L1 DDR2_DQ1 G2 DQ1 K2 DDR2_DQ2 H7 DQ2 K1 DDR2_DQ3 H3 DQ3
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Chapter 1: SP601 Evaluation Board Table 1-5: DDR2 Component Memory Connections (Cont’d) Memory U2 FPGA U1 Schematic Netname Pin Number Name F2 DDR2_BA0 L2 BA0 F1 DDR2_BA1 L3 BA1 E1 DDR2_BA2 L1 BA2 E3 DDR2_WE_B K3 WE L5 DDR2_RAS_B K7 RAS K5 DDR2_CAS_B L7 CAS K6 DDR2_ODT K9 ODT G3 DDR2_CLK_P J8 CK G1 DDR2_CLK_N K8 CK H7 DDR2_CKE K2 CKE L4 DDR2_LDQS_P F7 LDQS L3 DDR2_LDQS_N E8 LDQS P2 DDR2_UDQS_P B7 UDQS P1 DDR2_UDQS_N A8 UDQS K3 DDR2_LDM F3 LDM K4 DDR2_UDM B3 UDM Figure 1-3 provides the user const
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Detailed Description Figure 1-4 provides the UCF constraints for the DDR2 SDRAM data pins, including the I/O pin assignment and I/O standard used. X-Ref Target - Figure 1-4 NET "DDR2_DQ15" LOC ="U1";| IOSTANDARD = SSTL18_II ; NET "DDR2_DQ14" LOC ="U2";| IOSTANDARD = SSTL18_II ; NET "DDR2_DQ13" LOC ="T1";| IOSTANDARD = SSTL18_II ; NET "DDR2_DQ12" LOC ="T2";| IOSTANDARD = SSTL18_II ; NET "DDR2_DQ11" LOC ="N1";| IOSTANDARD = SSTL18_II ; NET "DDR2_DQ10" LOC ="N2";| IOSTANDARD = SSTL18_II ; NET "DDR
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Chapter 1: SP601 Evaluation Board 3. SPI x4 Flash The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash through a 2.5V bank. The XC6SLX16-2CSG324 is a master device when accessing an external SPI flash memory device. The SP601 SPI interface has two parallel connected configuratio
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Detailed Description X-Ref Target - Figure 1-7 U1 FPGA SPI INTERFACE J12 U17 DIN,DOUT,CCLK SPI X4 FLASH MEMORY SPIX4_CS_B SPI_CS_B WINBOND W25Q64VSFIG 2 1 ON = SPI X4 U17 SPI PROGRAM OFF = SPI EXT. J12 J15 HEADER SPI SELECT JUMPER UG518_07_070809 Figure 1-7: SPI Flash Interface Topology Table 1-6: SPI x4 Memory Connections SPI MEM U17 SPI HDR J12 FPGA U1 Schematic Netname Pin Pin # Pin Name Pin # Pin Name V2 FPGA_PROG_B 1 V14 FPGA_D2_MISO3 1 IO3_HOLD_B 2 T14 FPGA_D1_MISO2_R 9 IO2_WP_B 3 V3 SPI
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Chapter 1: SP601 Evaluation Board Figure 1-8 provides the UCF constraints for the SPI serial flash PROM. X-Ref Target - Figure 1-8 NET "FPGA_D2_MISO3" LOC = "V14"; NET "SPI_CS_B" LOC = "V3"; NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13"; NET "FPGA_D1_MISO2" LOC = "T14"; NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13"; NET "FPGA_CCLK" LOC = "R15"; Figure 1-8: UCF Location Constraints for BPI Flash Connections References Se
