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MAX12557
19-3544; Rev 0; 2/05
Dual, 65Msps, 14-Bit, IF/Baseband ADC
General Description Features
The MAX12557 is a dual 3.3V, 14-bit analog-to-digital
♦ Direct IF Sampling Up to 400MHz
converter (ADC) featuring fully differential wideband
♦ Excellent Dynamic Performance
track-and-hold (T/H) inputs, driving internal quantizers.
74.1dB/72.5dB SNR at f = 70MHz/175MHz
The MAX12557 is optimized for low power, small size, IN
83.4dBc/79.5dBc SFDR at f = 70MHz/175MHz
and high dynamic performance in inte
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Dual, 65Msps, 14-Bit, IF/Baseband ADC ABSOLUTE MAXIMUM RATINGS V to GND ................................................................-0.3V to +3.6V DD DIFFCLK/SECLK, G/T, PD, SHREF, DIV2, OV to GND............-0.3V to the lower of (V + 0.3V) and +3.6V DIV4 to GND .........-0.3V to the lower of (V + 0.3V) and +3.6V DD DD DD INAP, INAN to GND ...-0.3V to the lower of (V + 0.3V) and +3.6V DD D0A–D13A, D0B–D13B, DAV, INBP, INBN to GND ...-0.3V to the lower of (V + 0.3V) and +3.6V DORA, DORB to
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MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen- DD DD L IN tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f = 65MHz, T = -40°C to DD CLK A +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS f = 3MHz at -0.5dBFS (Note 3) 71.8 74.4 I
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Dual, 65Msps, 14-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen- DD DD L IN tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f = 65MHz, T = -40°C to DD CLK A +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Clock Overdrive Recovery Time ±10% beyond full sca
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MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen- DD DD L IN tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f = 65MHz, T = -40°C to DD CLK A +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I REFAP REF_P Sink Current V = 2.418V 1.2
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Dual, 65Msps, 14-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen- DD DD L IN tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f = 65MHz, T = -40°C to DD CLK A +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS D 0A–D13 A, DO RA, D 0B–D13 B and D ORB Tri - S
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MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen- DD DD L IN tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f = 65MHz, T = -40°C to DD CLK A +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS (Figure 5) Clock P
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Dual, 65Msps, 14-Bit, IF/Baseband ADC Typical Operating Characteristics (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C ≈ 5pF at digital outputs, V = -0.5dBFS, IN DD DD L DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f = 65MHz (50% duty cycle), T = +25°C, unless otherwise noted.) DD CLK A TWO-TONE IMD PLOT TWO-TONE IMD PLOT FFT PLOT (32,768-POINT DATA RECORD) (16,384-POINT DATA RECORD) (16,384-POINT DATA RECORD) 0 0 0 f = 65.00352MHz f = 65.00352MHz CLK f = 65
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MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC Typical Operating Characteristics (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C ≈ 5pF at digital outputs, V = -0.5dBFS, IN DD DD L DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f = 65MHz (50% duty cycle), T = +25°C, unless otherwise noted.) DD CLK A SNR, SINAD vs. CLOCK SPEED -THD, SFDR vs. ANALOG INPUT AMPLITUDE SNR, SINAD vs. ANALOG INPUT AMPLITUDE (f = 65.00352MHz, f = 175MHz) (f = 70MHz, A = -0.5dBFS) (f = 6
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Dual, 65Msps, 14-Bit, IF/Baseband ADC Typical Operating Characteristics (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C ≈ 5pF at digital outputs, V = -0.5dBFS, IN DD DD L DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f = 65MHz (50% duty cycle), T = +25°C, unless otherwise noted.) DD CLK A -THD, SFDR vs. ANALOG SUPPLY VOLTAGE SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE -THD, SFDR vs. DIGITAL SUPPLY VOLTAGE (f = 65.00352MHz, f = 175MHz) (f = 65.00352MHz, f = 70MHz) (f
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MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC Typical Operating Characteristics (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C ≈ 5pF at digital outputs, V = -0.5dBFS, IN DD DD L DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f = 65MHz (50% duty cycle), T = +25°C, unless otherwise noted.) DD CLK A SNR, SINAD vs. TEMPERATURE -THD, SFDR vs. TEMPERATURE (f = 175MHz, A = -0.5dBFS) (f = 175MHz, A = -0.5dBFS) IN IN IN IN 76 90 SNR 74 85 72 SFDR 80 70 SINAD 75 68 66
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Dual, 65Msps, 14-Bit, IF/Baseband ADC Pin Description PIN NAME FUNCTION 1, 4, 5, 9, GND Converter Ground. Connect all ground pins and the exposed paddle (EP) together. 13, 14, 17 2 INAP Channel A Positive Analog Input 3 INAN Channel A Negative Analog Input 6 COMA Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor. Channel A Positive Reference I/O. Channel A conversion range is ±2/3 x (V - V ). Bypass REFAP REFAN REFAP with a 0.1µF capacitor to GND. Connect a 10µF and a
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MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC Pin Description (continued) PIN NAME FUNCTION 28 D0B Channel B CMOS Digital Output, Bit 0 (LSB) 29 D1B Channel B CMOS Digital Output, Bit 1 30 D2B Channel B CMOS Digital Output, Bit 2 31 D3B Channel B CMOS Digital Output, Bit 3 32 D4B Channel B CMOS Digital Output, Bit 4 33 D5B Channel B CMOS Digital Output, Bit 5 34 D6B Channel B CMOS Digital Output, Bit 6 35 D7B Channel B CMOS Digital Output, Bit 7 36 D8B Channel B CMOS Digital Output, Bit 8 37 D9
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Dual, 65Msps, 14-Bit, IF/Baseband ADC Pin Description (continued) PIN NAME FUNCTION Power-Down Digital Input. 65 PD PD = GND: ADCs are fully operational. PD = OV : ADCs are powered down. DD Shared Reference Digital Input. SHREF = V : Shared reference enabled. DD SHREF = GND: Shared reference disabled. 66 SHREF When sharing the reference, externally connect REFAP and REFBP together to ensure that V = REFAP V . Similarly, when sharing the reference, externally connect REFAN to REFBN together to en
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MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC CLOCK 14-BIT DIGITAL D0A TO D13A INAP DATA OUTPUT T/H PIPELINE ERROR DRIVERS FORMAT ADC INAN CORRECTION DORA REFAP CHANNEL A REFERENCE COMA MAX12557 SYSTEM REFAN G/T REFIN INTERNAL REFERENCE REFOUT DAV GENERATOR SHREF OV DD REFBP CHANNEL B REFERENCE COMB SYSTEM REFBN INBP 14-BIT D0B TO D13B DIGITAL OUTPUT DATA T/H PIPELINE ERROR FORMAT DRIVERS INBN ADC DORB CORRECTION CLOCK V DD DIFFCLK/SECLK CLOCK POWER CLKP CLOCK CONTROL DUTY-CYCLE PD AND DIVIDER
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Dual, 65Msps, 14-Bit, IF/Baseband ADC Table 1. Reference Modes V DD V REFERENCE MODE BOND WIRE REFIN INDUCTANCE MAX12557 Internal Reference Mode. 1.5nH IN_P REFIN is driven by REFOUT either through a 35% V REFOUT C *C PAR SAMPLE direct short or a resistive divider. 2pF 4.5pF to 100% V = V / 2 COM_ DD V REFOUT V = V / 2 + 3/8 x V REF_P DD REFIN V DD BOND WIRE V = V / 2 - 3/8 x V REF_N DD REFIN INDUCTANCE 1.5nH Buffered External Reference Mode. IN_N An external 0.7V to 2.3V reference voltage is *C
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MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC to GND. Bypass REF_P to REF_N with a 10µF capacitor. The clock duty-cycle equalizer uses a delay-locked Bypass REFIN and REFOUT to GND with a 0.1µF capac- loop (DLL) to create internal timing signals that are itor. The REFIN input impedance is very large (>50MΩ ). duty-cycle independent. Due to this DLL, the When driving REFIN through a resistive divider, use MAX12557 requires approximately 100 clock cycles to resistances ≥10kΩ to avoid loading REFO
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Dual, 65Msps, 14-Bit, IF/Baseband ADC Table 2. Clock-Divider Control Inputs V DD DIV4 DIV2 FUNCTION S 1H Clock Divider Disabled MAX12557 00 f = f SAMPLE CLK 10kΩ Divide-by-Two Clock Divider 01 f = f / 2 SAMPLE CLK CLKP Divide-by-Four Clock Divider 10 10kΩ f = f / 4 SAMPLE CLK S DUTY-CYCLE 2H EQUALIZER 11 Not Allowed S 1L 10k Ω cuitry can be latched with the rising edge of the con- CLKN version clock (CLKP - CLKN). 10kΩ Data-Valid Output DAV is a single-ended version of the input clock that is
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MAX12557 Dual, 65Msps, 14-Bit, IF/Baseband ADC externally isolates it from heavy capacitive loads. Refer the falling edge of DAV and are valid on the rising edge to the MAX12557 EV kit schematic for recommendations of DAV. of how to drive the DAV signal through an external buffer. The MAX12557 output data format is either Gray code or two’s complement depending on the logic input G/T. Data Out-of-Range Indicator With G/T high, the output data format is Gray code. The DORA and DORB digital output
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Dual, 65Msps, 14-Bit, IF/Baseband ADC 1 LSB = 4/3 x (V - V ) / 16,384 1 LSB = 4/3 x (V - V ) / 16,384 REFP REFN REFP REFN 2/3 x (V - V ) 2/3 x (V - V ) 2/3 x (V - V ) 2/3 x (V - V ) REFP REFN REFP REFN REFP REFN REFP REFN 0x1FFF 0x2000 0x1FFE 0x2001 0x1FFD 0x2003 0x0001 0x3001 0x0000 0x3000 0x3FFF 0x1000 0x2003 0x0002 0x2002 0x0003 0x2001 0x0001 0x2000 0x0000 -8191 -8189 -1 0 +1 +8189 +8191 -8191 -8189 -1 0 +1 +8189 +8191 DIFFERENTIAL INPUT VOLTAGE (LSB) DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 6
