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SED1520 Series
LCD driver with RAM
Technical Manual
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NOTICE No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level
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CONTENTS Selection Guide 1. SED1510 Series 2. SED1520 Series 3. SED152A Series 4. SED1526 Series 5. SED1530 Series 6. SED1540 Series 7. SED1560 Series 8. SED1565 Series 9. SED1570 Series
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SED1500 Series Selection Guide
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n LCD drivers with RAM for small- Ultra-low power consumption and on-chip RAM make this series ideal for compact and medium-sized displays LCD-based equipment. SED1500 series Supply voltage LCD voltage Display Microprocessor Frequency Application/additional Part number Duty Segment Common Package range (V) range (V) RAM (bits) interface (KHz) features SED1510D0C AI pad chip Small segment-type LCD SED1510D0B Au bump chip display. Command and data SED1510F0C 0.9–6.0 1.8–6.0 1/4 32 4 128 Serial 18
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Supply voltage LCD voltage Display Microprocessor Frequency Application/additional Part number Duty Segment Common Package range (V) range (V) RAM (bits) interface (KHz) features SED1560D0A Al pad chip SED1560DAA Al pad chip SED1560D0B 1/48, 1/49 Au bump chip 102 65 SED1560DAB 1/64, 1/65 Au bump chip SED1560T0B TCP SED1560TQA QTCP SED1561D0A Al pad chip Built-in power circuit for LCD (voltage tripler) SED1561DAA 166×65 Al pad chip SED1560] 0B (1/9 bias) 18 SED1561D0B 2.4–6.0 6.0–16.0 bits Au bum
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Supply voltage LCD voltage Display Microprocessor Frequency Application/additional Part number Duty Segment Common Package range (V) range (V) RAM (bits) interface (KHz) features SED1530D0A Al pad chip SED1530DAA Al pad chip Au bump chip SED1530D0B 1/32, 1/33 100 33 SED1530DAB Au bump chip SED1530TAA TCP Built-in power circuit for LCD (voltage quadrupler) SED1531D0A Al pad chip SED153]] 0] SED1531D0B 132 – Au bump chip (Common: Right side) 132×65 8-bit parallel SED153]] A] TCP SED1531T0A 2.4–6.
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2. SED1520 Series
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SED1520 Series Contents OVERVIEW ..........................................................................................................................................................2-1 FEATURES ...........................................................................................................................................................2-1 BLOCK DIAGRAM ...............................................................................................................................
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SED1520 Series OVERVIEW FEATURES The SED1520 family of dot matrix LCD drivers are • Fast 8-bit MPU interface compatible with 80- and 68- designed for the display of characters and graphics. The family microcomputers drivers generate LCD drive signals derived from bit • Many command set mapped data stored in an internal RAM. • Total 80 (segment + common) drive sets The drivers are available in two configurations • Low power — 30 μW at 2 kHz external clock The SED1520 family drivers incorporate i
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SED1520 Series BLOCK DIAGRAM An example of SED1520 AA: * LCD drive circuit Common counter Display data latch circuit Display data RAM (2560-bit) Column address decoder CL Display timing Column address counter FR generator circuit Column address register Command Status decoder MPU interface 2–2 EPSON Display start line register Line counter V1,V2,V3,V4,V5 Line address decoder D0~D7 COM0 to COM15 A0,CS RD,WR (E,R/W) SEG0 to SEG60 M/S RES Low-address I/O buffer Bus VDD register holder VSS
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SED1520 Series PACKAGE OUTLINE QFP5 CS2 SEG22 CS3 SEG23 CS4 SEG24 CS5 SEG25 CS6 SEG26 85 CS7 45 SEG27 VDD SEG28 SEG29 RES SEG30 F2 90 SEG31 V5 40 SEG32 V1 SEG33 V2 Index SEG34 M/S SEG35 V4 95 SEG36 V1 35 SEG37 COM0 SEG38 COM1 SEG39 COM2 SEG40 COM3 100 SEG41 COM4 QFP15 50 VSS SEG20 D30 SEG21 D31 SEG22 D32 SEG23 D33 80 SEG24 46 D34 45 SEG25 D35 SEG26 D36 SEG27 D37 SEG28 VDD 85 SEG29 RES 40 SEG30 F R SEG31 V5 SEG32 V3 SEG33 V2 90 SEG34 M/S 35 SEG35 V4 SEG36 V1 SEG37 COM 0 SEG38 COM 1 95 SEG39 COM
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SED1520 Series PAD Pad Arrangement Chip specifications of AL pad package Chip specifications of gold bump package Chip size: 4.80×7.04×0.400 mm Chip size: 4.80×7.04×0.525 mm Pad pitch: 100×100 μm Bump pitch: 199 μm (Min.) Bump height: 22.5 μm (Typ.) Bump size: 132×111 μm (±20 μm) for mushroom model 116×92 μm (±4 μm) for vertical model 100 95 90 85 80 1 5 75 10 Y 70 X 15 (0, 0) 65 20 60 25 55 30 35 40 45 50 4.80 mm Note: An example of SED1520DAA die numbers is given. These numbers are the same a
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SED1520 Series PAD ARRANGEMENT An example of SED1520DA pin names is given. The * asterisk ( ) can be A for AL pad package or B for gold * bump package. SED1520DAB Pad Center Coordinates Pad Pin Pad Pin Pad Pin XY XY XY No. Name No. Name No. Name 1 COM5 159 6507 35 SEG37 1302 159 69 SEG3 4641 4148 2 COM6 159 6308 36 SEG36 1502 159 70 SEG2 4641 4347 3 COM7 159 6108 37 SEG35 1701 159 71 SEG1 4641 4547 4 COM8 159 5909 38 SEG34 1901 159 72 SEG0 4641 4789 5 COM9 159 5709 39 SEG33 2100 159 73 A0 4641
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SED1520 Series PIN DESCRIPTION (1) Power Pins Name Description VDD Connected to the +5Vdc power. Common to the VCC MPU power pin. VSS 0 Vdc pin connected to the system ground. V1, V2, V3, V4, V5 Multi-level power supplies for LCD driving. The voltage determined for each liquid crystal cell is divided by resistance or it is converted in impedance by the op amp, and supplied. These voltages must satisfy the following: VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 (2) System Bus Connection Pins D7 to D0 Three-
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SED1520 Series (3) LCD Drive Circuit Signals Name Description CL Input. Effective for an external clock operation model only. This is a display data latch signal to count up the line counter and common counter at each signal falling and rising edges. If the system has a built-in oscillator, this is used as an output pin of the oscillator amp and an Rf oscillator resistor is con- nected to it. FR Input/output. This is an I/P pin of LCD AC signals, and connected to the M terminal of common driv
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SED1520 Series BLOCK DESCRIPTION System Bus MPU interface 1. Selecting an interface type level after reset (see Table 1). The SED1520 series transfers data via 8-bit bidirec- When the CS signal is high, the SED1520 series is tional data buses (D0 to D7). As its Reset pin has the disconnected from the MPU bus and set to stand by. MPU interface select function, the 80-series MPU or However, the reset signal is entered regardless of the the 68-series MPU can directly be connected to the internal s
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SED1520 Series WRITE WR MPU DATA N N + 1 N + 2 N + 3 Bus Internal N N + 1 N + 2 N + 3 timing hold WR READ WR RD MPU DATA N N n n + 1 Address set Dummy read Data read Data read at N at N at N + 1 WR RD Internal timing Column N N + 1 N + 2 address Bus N n n + 1 n + 2 hold Figure 1 Bus Buffer Delay Busy flag Column Address Counter When the Busy flag is logical 1, the SED1520 series is The column address counter is a 7-bit presettable counter executing its internal operations. Any command other t
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SED1520 Series Common Timing Generator Circuit Generates common timing signals and FR frame signals from the CL basic clock. The 1/16 or 1/32 duty (for SED1520) or 1/8 or 1/16 duty (for SED1522) can be selected by the Duty Select command. If the 1/32 duty is selected for the SED1520 and 1/16 duty is selected for the SED1522, the 1/32 and 1/16 duties are provided by two chips consisting of the master and slave chips in the common multi-chip mode. SED1520 FR signal (Master output) 01 2 1415 0 1
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SED1520 Series Oscillator Circuit (SED1520 0A Only) * A low power-consumption CR oscillator for adjusting the oscillation frequency using Rf oscillation resistor only. This circuit generates a display timing signal. Some of SED1520 and SED1522 series models have a built-in oscillator and others use an external clock. This difference must be checked before use. Connect the Rf oscillation resistor as follows. To sup- press the built-in oscillator circuit and drive the MPU using an external cloc
