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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined Sync SRAM
[1]
Features Functional Description
• Supports bus operation up to 250 MHz The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM
integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with
• Available speed grades are 250, 200 and 167 MHz
advanced synchronous peripheral circuitry and a two-bit
• Registered inputs and outputs for pipelined operation
counter for internal burst operation. All synchronous inputs
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Logic Block Diagram – CY7C1440AV33 (1M x 36) A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV Q1 CLK BURST COUNTER CLR AND Q0 LOGIC ADSC ADSP DQD ,DQPD DQD ,DQPD BYTE BYTE BWD WRITE REGISTER WRITE DRIVER DQC ,DQPC DQC ,DQPC BYTE BWC BYTE OUTPUT WRITE DRIVER OUTPUT WRITE REGISTER MEMORY SENSE DQs BUFFERS ARRAY REGISTERS AMPS DQPA DQB ,DQPB E DQB ,DQPB DQPB BYTE BYTE BWB DQPC WRITE DRIVER WRITE REGISTER DQPD DQA ,DQPA DQA ,DQPA BYTE BYTE BWA WR
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Logic Block Diagram – CY7C1446AV33 (512K x 72) ADDRESS A0, A1,A REGISTER A[1:0] MODE ADV Q1 BINARY CLK COUNTER CLR Q0 ADSC ADSP DQH, DQPH DQH, DQPH BWH WRITE DRIVER WRITE DRIVER DQF, DQPF DQG, DQPG BWG WRITE DRIVER WRITE DRIVER DQF, DQPF DQF, DQPF BWF WRITE DRIVER WRITE DRIVER DQ BYTE E, DQP “a”E DQE, DQPE BWE WRITE DRIVER WRITE DRIVER WRITE DRIVER MEMORY ARRAY DQD, DQPD DQD, DQPD BWD WRITE DRIVER WRITE DRIVER DQC, DQPC DQC, DQPC BWC WRITE DRIVER WRITE DR
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Pin Configurations 100-pin TQFP Pinout DQP C 1 80 DQPB NC A 1 80 DQC 2 79 DQB NC NC 2 79 DQc 3 78 DQB NC NC 3 78 V DDQ V 4 77 V DDQ DDQ 4 77 V DDQ V SSQ V 5 76 V SSQ SSQ 5 76 V SSQ DQC DQB 6 75 NC 6 75 NC DQC DQB 7 74 NC 7 74 DQPA DQC DQB 8 73 DQB 8 73 DQA DQC 9 72 DQB DQB DQA 9 72 V SSQ 10 71 V SSQ V SSQ V 10 71 SSQ V DDQ 11 70 V DDQ V DDQ V 11 70 DDQ DQC 12 69 DQB DQB DQA 12 69 DQC DQB 13 68 DQB DQA 13 68 NC V 14 67 NC SS 14 67 V SS V DD NC 15 66 V DD
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1440AV33 (1M x 36) 1 23 4 5 6 7 89 10 11 A NC/288M CE BW BW CE ADSC A NC A BWE ADV 1 C B 3 B NC/144M A CE2 BW BW CLK GW OE ADSP A NC/576M D A DQP NC V V V V V V V NC/1G DQP C C DDQ SS SS SS SS SS DDQ B D DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B E DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ F C DD SS DD B C DDQ SS SS DDQ B D
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Pin Configurations (continued) 209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1446AV33 (512K × 72) 123456789 10 11 A DQ DQ A CE ADSC ADSP ADV A 2 CE DQ G G DQ 3 B B B DQ DQ G A BWS G BWS NC/288M BW BWS DQ DQ BWS B C F B G B C DQ DQ NC/144M G NC/576M BWS BWS BWS CE BWS DQ G E DQ H D 1 A B B D DQ NC DQ V NC/1G OE GW V G G SS NC DQ SS DQ B B E DQP DQP V V V V V V V G C DDQ DDQ DD DD DD DDQ DDQ DQP DQP F B F DQ C DQ V V V V NC V V DQ C SS SS SS SS SS F DQ SS F
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Pin Definitions (continued) Name I/O Description CE Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction 2 Synchronous with CE and CE to select/deselect the device. CE is sampled only when a new external 1 3 2 address is loaded. CE Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction 3 Synchronous with CE and CE to select/deselect the device. Not available for AJ pack
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 then the Write operation is controlled by BWE and BW Functional Overview X signals. All synchronous inputs pass through input registers controlled The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 by the rising edge of the clock. All data outputs pass through provides Byte Write capability that is described in the Write output registers controlled by the rising edge of the clock. Cycle Descriptions table. Asserting the Byte Write Enable Maximum access delay from
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Interleaved Burst Address Table Linear Burst Address Table (MODE = GND) (MODE = Floating or V ) DD First Second Third Fourth First Second Third Fourth Address Address Address Address Address Address Address Address A1: A0 A1: A0 A1: A0 A1: A0 A1: A0 A1: A0 A1: A0 A1: A0 00 01 10 11 00 01 10 11 01 10 11 00 01 00 11 10 10 11 00 01 10 11 00 01 11 00 01 10 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 [2, 3, 4, 5, 6, 7] Truth Table (continued) Operation Add. Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D [4,8,9] Truth Table for Read/Write Funct
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 [4, 8, 9] Truth Table for Read/Write Function (CY7C1446AV33) GW BWE BW X Read HH X Read H L All BW = H Write Byte x – (DQ and DQP)HLL x x Write All Bytes H L All BW = L Write All Bytes L X X Test Access Port (TAP) IEEE 1149.1 Serial Boundary Scan (JTAG) Test Clock (TCK) The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 incor- porates a serial boundary scan test access port (TAP). This The test clock is used only with the TAP controller. All inputs part is fully
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Performing a TAP Reset TAP Instruction Set A RESET is performed by forcing TMS HIGH (V ) for five DD Overview rising edges of TCK. This RESET does not affect the operation Eight different instructions are possible with the three bit of the SRAM and may be performed while the SRAM is instruction register. All combinations are listed in the operating. Instruction Codes table. Three of these instructions are listed At power-up, the TAP is reset internally to
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 The shifting of data for the SAMPLE and PRELOAD phases The boundary scan register has a special bit located at, bit #89 can occur concurrently when required—that is, while data (for 165-FBGA package) or bit #138 (for 209-FBGA package). captured is shifted out, the preloaded data can be shifted in. When this scan cell, called the “extest output bus tri-state”, is latched into the preload register during the “Update-DR” state BYPASS in the TAP controller, i
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 [10, 11] TAP AC Switching Characteristics Over the operating Range Parameter Description Min. Max. Unit Clock t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH time 20 ns TH t TCK Clock LOW time 20 ns TL Output Times t TCK Clock LOW to TDO Valid 10 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX Set-up Times t TMS Set-up to TCK Clock Rise 5 ns TMSS t TDI Set-up to TCK Clock Rise 5 ns TDIS t Capture Set-up to TCK Rise 5 ns
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 TAP DC Electrical Characteristics And Operating Conditions [12] (0°C < TA < +70°C; V = 3.135 to 3.6V unless otherwise noted) DD Parameter Description Test Conditions Min. Max. Unit V Output HIGH Voltage I = –4.0 mA, V = 3.3V 2.4 V OH1 OH DDQ I = –1.0 mA, V = 2.5V 2.0 V OH DDQ V Output HIGH Voltage I = –100 µA V = 3.3V 2.9 V OH2 OH DDQ V = 2.5V 2.1 V DDQ V Output LOW Voltage I = 8.0 mA V = 3.3V 0.4 V OL1 OL DDQ I = 1.0 mA V = 2.5V 0.4 V OL DDQ V Outp
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Identification Codes (continued) Instruction Code Description SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. [14,15] 165-
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 [14, 16] 209-ball FBGA Boundary Scan Order CY7C1446AV33 (512K x 72) Bit # ball ID Bit # ball ID Bit # ball ID Bit # ball ID 1 36 F6 71 106 K3 W6 H6 2 37 K8 72 C6 107 K4 V6 3 U6 38 K9 73 B6 108 K6 4 W7 39 K10 74 A6 109 K2 5V7 40 J11 75 A5 110 L2 6 U7 41 J10 76 B5 111 L1 7T7 42 H11 77 C5 112 M2 8 V8 43 H10 78 D5 113 M1 9 U8 44 G11 79 D4 114 N2 10 T8 45 G10 80 C4 115 N1 11 V9 46 F11 81 A4 116 P2 12 U9 47 F10 82 B4 117 P1 13 P6 48 E10 83 C3 118 R2 14 W11 4
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage.......................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current......................
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 [19] Capacitance 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Max. Max. Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 6.5 7 5 pF IN A V = 3.3V DD C Clock Input Capacitance 3 7 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5.5 6 7 pF I/O [19] Thermal Resistance 100 TQFP 165 FBGA 209 FBGA Unit Parameter Description Test Conditions Package Package Package Θ Thermal Resistance Test conditions follow standard 25.21 20.8 25.31 °C/W
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CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 [24, 25] Switching Characteristics Over the Operating Range –250 –200 –167 Parameter Description Min. Max Min. Max. Min. Max Unit [20] t V (Typical) to the first Access 111ms POWER DD Clock t Clock Cycle Time 4.0 5 6 ns CYC t Clock HIGH 1.5 2.0 2.4 ns CH t Clock LOW 1.5 2.0 2.4 ns CL Output Times t Data Output Valid After CLK Rise 2.6 3.2 3.4 ns CO t Data Output Hold After CLK Rise 1.0 1.5 1.5 ns DOH [21, 22, 23] t Clock to Low-Z 1.0 1.3 1.5 ns CLZ [21,
