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CY7C1365C
9-Mbit (256K x 32) Flow-Through Sync SRAM
[1]
Features Functional Description
• 256K x 32 common I/O
The CY7C1365C is a 256K x 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
• 3.3V core power supply (V )
DD
minimum glue logic. Maximum access delay from clock rise is
• 2.5V/3.3V I/O power supply (V )
DDQ
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
• Fast clock-to-output times
first address in a burst and increments the address au
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CY7C1365C Logic Block Diagram-CY7C1365C (256K x 32) ADDRESS A0, A1, A REGISTER A[1:0] MODE ADV Q1 BURST CLK COUNTER AND LOGIC Q0 CLR ADSC ADSP DQD DQD BYTE BWD BYTE BYTE WRITE REGISTER WRITE REGISTER WRITE REGISTER DQC DQC BWC BYTE BYTE WRITE REGISTER WRITE REGISTER OUTPUT DQs MEMORY SENSE BUFFERS ARRAY DQB AMPS DQB BYTE BWB BYTE WRITE REGISTER WRITE REGISTER DQA BYTE DQA BWA BYTE WRITE REGISTER BWE WRITE REGISTER INPUT GW REGISTERS ENABLE CE1 REGISTER CE2 CE3 OE SLEEP ZZ CONTROL Documen
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CY7C1365C Pin Configurations 100-Pin TQFP Pinout (2 Chip Enable) (AJ version) NC 1 80 NC DQ 2 C 79 DQ B DQ 3 DQ C 78 B V 4 V DDQ 77 DDQ V 5 V SSQ 76 SSQ DQ 6 C 75 DQ B DQ 7 C 74 DQ B DQ 8 BYTE C C 73 DQ BYTE B B DQ 9 C 72 DQ B V 10 SSQ 71 V SSQ V 11 DDQ 70 V DDQ DQ 12 C 69 DQ B DQ 13 C 68 DQ B NC 14 67 V SS CY7C1365C V 15 NC DD 66 NC 16 65 V DD V 17 ZZ SS 64 DQ 18 DQ D 63 A DQ 19 62 DQ D A V 20 DDQ 61 V DDQ V 21 SSQ 60 V SSQ DQ 22 D 59 DQ A BYTE D BYTE A DQ 23 D 58 DQ A DQ 24 D 57 DQ A DQ 2
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CY7C1365C Pin Configurations (continued) 100-Pin TQFP Pinout (3 Chip Enable) (A version) NC 1 80 NC DQ 2 C 79 DQ B DQ 3 DQ C 78 B V 4 V DDQ 77 DDQ V 5 V SSQ 76 SSQ DQ 6 C 75 DQ B DQ 7 C 74 DQ B DQ 8 BYTE C C 73 DQ BYTE B B DQ 9 C 72 DQ B V 10 SSQ 71 V SSQ V 11 DDQ 70 V DDQ DQ 12 C 69 DQ B DQ 13 C 68 DQ B NC 14 67 V SS CY7C1365C V 15 NC DD 66 NC 16 65 V DD V 17 ZZ SS 64 DQ 18 DQ D 63 A DQ 19 62 DQ D A V 20 DDQ 61 V DDQ V 21 SSQ 60 V SSQ DQ 22 D 59 DQ A BYTE D BYTE A DQ 23 D 58 DQ A DQ 24 D 57
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CY7C1365C Pin Descriptions Name TQFP I/O Description A0, A1, A 37,36,32,33,34,35,44,45,46, Input- Address Inputs used to select one of the 256K address 47,48,49,50,81,82,99,100 Synchronous locations. Sampled at the rising edge of the CLK if ADSP or ADSC 92 (for 2 Chip Enable Version) is active LOW, and CE , CE , and CE are sampled active. A feed 1 2 3 [1:0] 43 (for 3 Chip Enable Version) the 2-bit counter. BW BW 93,94, Input- Byte Write Select Inputs, active LOW. Qualified with BWE to A,
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CY7C1365C Pin Descriptions (continued) Name TQFP I/O Description V 15,41,65, 91 Power Supply Power supply inputs to the core of the device. DD V 17,40,67,90 Ground Ground for the core of the device. SS V 4,11,20,27,54,61,70,77 I/O Power Power supply for the I/O circuitry. DDQ , Supply V 5,10,21,26,55,60,71,76 I/O Ground Ground for the I/O circuitry. SSQ MODE 31 Input- Selects Burst Order. When tied to GND selects linear burst Static sequence. When tied to V or left floating selects interl
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CY7C1365C active, (2) ADSC is asserted LOW, (3) ADSP is deasserted Functional Overview HIGH, and (4) the write input signals (GW, BWE, and BW[A:D]) All synchronous inputs pass through input registers controlled indicate a write access. ADSC is ignored if ADSP is active by the rising edge of the clock. Maximum access delay from LOW. the clock rise (t ) is 6.5 ns (133-MHz device). CDV The addresses presented are loaded into the address register The CY7C1365C supports secondary cache in systems
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CY7C1365C ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I Sleep mode standby current ZZ > V – 0.2V 50 mA DDZZ DD t Device operation to ZZ ZZ > V – 0.2V 2t ns ZZS DD CYC t ZZ recovery time ZZ < 0.2V 2t ns ZZREC CYC t ZZ Active to Sleep current This parameter is sampled 2t ns ZZI CYC t ZZ Inactive to exit Sleep current This parameter is sampled 0 ns RZZI [3, 4, 5, 6, 7] Truth Table Address Cycle Description Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ
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CY7C1365C [3, 4] Truth Table for Read/Write Function GW BWE BW BW BW BW D C B A Read H H XXXX Read H L HHHH Write Byte (A, DQP) H L HHH L A Write Byte (B, DQP)HLHHLH B Write Bytes (B, A, DQP , DQP)H L H H L L A B Write Byte (C, DQP) H LH LH H C Write Bytes (C, A, DQP , DQP) H LH LH L C A Write Bytes (C, B, DQP , DQP)H L H L L H C B Write Bytes (C, B, A, DQP , DQP , DQP) H L H LLL C B A Write Byte (D, DQP) H L L HHH D Write Bytes (D, A, DQP , DQP)H L L H H L D A Write Bytes (D, B, DQP , DQP)H L
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CY7C1365C DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage........................................... >2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current...................................................
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CY7C1365C [10] Capacitance 100 TQFP Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 3.3V DD C Clock Input Capacitance 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 pF I/O [10] Thermal Resistance 100 TQFP Parameter Description Test Conditions Package Unit Θ Thermal Resistance Test conditions follow standard test 29.41 °C/W JA (Junction to Ambient) methods and procedures for measuring thermal impedance, per Θ Thermal Resistance 6.13
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CY7C1365C [11, 12] Switching Characteristics Over the Operating Range –133 –100 Parameter Description Min. Max. Min. Max. Unit [13] t V (Typical) to the First Access 11 ms POWER DD Clock t Clock Cycle Time 7.5 10 ns CYC t Clock HIGH 3.0 4.0 ns CH t Clock LOW 3.0 4.0 ns CL Output Times t Data Output Valid after CLK Rise 6.5 8.5 ns CDV t Data Output Hold after CLK Rise 2.0 2.0 ns DOH [14, 15, 16] t Clock to Low-Z 00 ns CLZ [14, 15, 16] t Clock to High-Z 3.5 3.5 ns CHZ t OE LOW to Output Valid 3
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CY7C1365C Timing Diagrams [17] Read Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP t t ADS ADH ADSC t t AH AS A1 A2 ADDRESS t t WES WEH GW, BWE,BW [A:D] Deselect Cycle t t CES CEH CE t t ADVS ADVH ADV ADV suspends burst. OE t t t CDV OEV OELZ t t OEHZ CHZ t DOH t CLZ Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Data Out (Q) High-Z Q(A1) t CDV Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 17. On this diagram, when CE is LOW, CE is
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CY7C1365C Timing Diagrams (continued) [18, 19] Write Cycle Timing t CYC CLK t t CL CH t t ADH ADS ADSP ADSC extends burst. t t ADS ADH t t ADH ADS ADSC t t AS AH ADDRESS A1 A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst. t t WES WEH BWE, BW[A:D] t t WES WEH GW t t CES CEH CE t t ADVS ADVH ADV ADV suspends burst. OE t t DS DH Data in (D) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) High-Z D(A1) t OEHZ Data Out (Q) BURST READ Single
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CY7C1365C Timing Diagrams (continued) [17, 19, 20] Read/Write Timing t CYC CLK t t CL CH t t ADH ADS ADSP ADSC t t AS AH ADDRESS A1 A2 A3 A4 A5 A6 t t WES WEH BWE, BW[A:D] t t CEH CES CE ADV OE t t DH DS t OELZ High-Z D(A3) D(A5) D(A6) Data In (D) t OEHZ t CDV Data Out (Q) Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back Back-to-Back READs Single WRITE BURST READ WRITEs DON’T CARE UNDEFINED Note: 20. GW is HIGH. Document #: 38-05690 Rev. *E Page 15 of 18 [+] Feedback
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CY7C1365C Timing Diagrams (continued) [21, 22] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 133 CY7C1365C-133AXC 51-85050 100-pin Thin Quad Fl
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CY7C1365C Package Diagram 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 1 80 0.30±0.08 0.65 12°±1° SEE DETAIL A TYP. (8X) 30 51 31 50 0.20 MAX. 1.60 MAX. R 0.08 MIN. 0° MIN. 0.20 MAX. SEATING PLANE STAND-OFF 0.05 MIN. NOTE: 0.25 0.15 MAX. 1. JEDEC STD REF MS-026 GAUGE PLANE 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE R 0.08 MIN. 0°-7° BODY LENGTH DIMENSIONS ARE MA
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CY7C1365C Document History Page Document Title: CY7C1365C 9-Mbit (256K x 32) Flow-Through Sync SRAM Document Number: 38-05690 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 286269 See ECN PCI New data sheet *A 320834 See ECN PCI Added 133 MHz in the Ordering Information table Changed Θ and Θ for TQFP Package from 25 and 9 °C/W to 29.41 and JA JC 6.13 °C/W respectively Modified V V test conditions OL, OH Corrected IDD, tCDV, tCH, tDOH and tCL for 100MHz to 180 mA, 8.5 ns,
